MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 380

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

IDMA Channels
7.6.5.3 AUTO BUFFER EXAMPLE. The previous buffer chaining example can be easily
modified to show the auto buffer operation. Simply set the CM bit in the BD_STATUS words
of each of the three BDs, and for the sake of clarity, clear the L-bit of the third BD. The IDMA
channel will then repeatedly transfer groups of 16 bytes until the STR bit is cleared in soft-
ware, the IDMA is reset, or the V-bit is cleared in one of the IDMA BDs.
7-56
22. BD2_Data_Length = $00000010. Transfer 16 bytes.
23. BD2_Source_Pointer = $00000100. Source address.
24. BD2_Destination_Pointer = $00001100. Destination address.
25. BD2_STATUS = $8000. Set the V-bit. It is good practice to set the V-bit last;
26. Initialize the third IDMA BD:
27. BD3_STATUS = $2800. This is offset 0 from the BD. Set up all bits except the
28. BD3_Data_Length = $00000010. Transfer 16 bytes.
29. BD3_Source_Pointer = $00000200. Source address.
30. BD3_Destination_Pointer = $00001200. Destination address.
31. BD3_STATUS = $A800. Set the V-bit. It is good practice to set the V-bit last;
32. Start the IDMA channel:
33. CMR1 = $530D. Set the STR bit of this register. The IDMA now begins
34. Check for successful completion:
35. Read the CMR and wait for the STR bit to be cleared, indicating the end of the
V-bit.
however, in this example the IDMA channel is not yet enabled, so it could have
been set earlier.
V-bit. In this case, set the L-bit to indicate that the IDMA should stop after this BD,
and set the DONE bit in the CSR. Additionally, set the W-bit to cause the RISC to
point to the first BD when done. The W-bit should always be set in the last BD of
the list.
however, in this example the IDMA channel is not yet enabled, so it could have
been set earlier.
transferring all three BDs.
transfer. Read the CSR to see what status has been set. In this case, only the
DONE bit should be set. The AD bit would only be set if the I-bit of the
BD_STATUS field had been set.
Use of the IDMA internal maximum rate option in the auto buffer
mode is not recommended because the CPU32+ would only be
able to execute instructions during the brief period that the RISC
is configuring the IDMA channel between BDs. These bits MUST
be set to 7 if the QUICC is in slave mode.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE