MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 658

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Parallel Interface Port (PIP)
Thus, to connect to QUICCs using this interface, connect the STBO pin of each QUICC to
the STBI pin of the other and connect the desired data pins (either PB8–PB15 or PB0–PB15
are connected between QUICCs).
7.13.5 Pulsed Data Transfers
In the pulsed handshake mode, the PIP may be configured as a transmitter or a receiver.
This configuration allows a Centronics-compatible interface to be implemented.
The pulsed handshake mode may be controlled by the RISC or the CPU32+ core. Operation
using the RISC requires BDs and parameter RAM initialization very similar to the other serial
channels. Data is then stored in the buffers using one of the SDMA channels (one of the
available channels from SMC2). Operation by the CPU32+ core is performed by software-
controlled reads and writes from/to the PIP data register upon interrupt request.
When configured as a transmitter, the STBO pin (PB16) is used as a strobe output (STB)
handshake control signal, and the STBI pin (PB17) is used as an acknowledge (ACK) input.
When configured as a receiver, the PIP generates the ACK signal on the STBO pin and
inputs the STB signal on the STBI pin.
Bits PB16 and PB17 in the port B data direction register (PBDIR) and the port B data register
(PBDAT) corresponding to STBO and STBI are not valid and are ignored by the PIP when
the pulsed handshake mode is selected.
7-334
(OUTPUT READY)
(INPUT READY)
TRANSMITTER
TRANSMITTER
RECEIVER
DATA
ACK
STB
At the time of writing, RISC operation of the PIP has not been
fully defined. The user should use the CPU32+ core operation
mode until as RISC microcode becomes available or the full PIP
microcode is available in the RISC internal ROM. Please contact
the local Motorola sales representative to obtain the current sta-
tus of the PIP RISC microcode. In the following description, the
RISC reads and writes of the data register are replaced by
CPU32+ core reads and writes.
Figure 7-85. Interlock Handshake Mode
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
T SETUP
Go to: www.freescale.com
NOTE
T HOLD