MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 742

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Applications
The RBASE and TBASE values are new to the QUICC. They point to the start of the buffer
descriptor tables, must be long-word aligned, and must point to the dual-port RAM area.
The RFCR and TFCR registers have one additional purpose and a different bit placement
on the QUICC. If RFCR and TFCR are cleared on the MC68302 or not used with the
MC68302, then the equivalent function on the QUICC can be implemented by writing $18 to
the QUICC RFCR and TFCR. Note that on the QUICC there is an additional function code
pin to signify DMA operation, and the suggestion of $18 uses this capability.
The MRBLR value has the same function on both devices. Additionally, if the receive FIFO
is set to 32-bit-wide mode, the MRBLR value must be aligned to a long word.
The internal state parameter has the same function on both devices.
The MC68302 RBD# and TBD# have the same concept on the QUICC, except the param-
eters are called RBPTR and TBPTR and are now 16-bit values. They point to the current
buffer descriptor; however, they are now offsets from the beginning location of the QUICC
dual-port RAM. For example, the current transmit buffer descriptor location may be found by
MBAR + TBPTR.
The internal data pointer parameter has the same function on both devices.
The internal byte count parameter has the same function on both devices.
9.3.4.2.3 Protocol-Dependent Parameter RAM Values. These values are very similar
between devices, although new functions are often added on the QUICC. Where possible,
any parameter for a given protocol that is the same for the MC68302 and the QUICC carries
the same name on both devices.
The following points note changes between the MC68302 and the QUICC protocol-depen-
dent parameter RAM for a given protocol:
9-22
In the UART mode, if the MAX_IDL entry is programmed to $0000 on the QUICC, the
function will be disabled.
In the UART mode, the ability to send special control characters, such as XOFF, no longer
requires the CHARACTER8 entry. Rather, a new entry, called the TOSEQ entry, has
been created. The programming of the TOSEQ entry, however, is the same as the old
MC68302 CHARACTER8 entry.
In UART mode, note the new parameters for a receive character mask (RCCM) and a
function that times the length of a receive break (BRKLN).
The HDLC parameter RAM is the same, except for two new entries: RFTHR and RFCNT.
They allow the user to reduce the number of received frame interrupts generated, and
should be used in higher data rate applications.
The BISYNC parameter RAM is unchanged.
DDCMP is a microcode RAM product on the QUICC. The port of DDCMP from the
MC68302 is not discussed.
V.110 is not supported on the QUICC.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com