IPSRAMQDRII Altera, IPSRAMQDRII Datasheet - Page 17

• Manufacturer Part Number: IPSRAMQDRII
• Manufacturer: Altera

Specifications of IPSRAMQDRII

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Figure 2–2. System Naming
Altera Corporation
November 2009
Other Logic
PLL
14. IP Toolbench uses a prefix (e.g., qdrii_) for the names of all memory
15. Click Finish.
Step 2: Constraints
To choose the constraints for your device, follow these steps:
1.
2.
Step 3: Set Up Simulation
An IP functional simulation model is a cycle-accurate VHDL or Verilog
HDL model produced by the Quartus II software. The model allows for
fast functional simulation of IP using industry-standard VHDL and
Verilog HDL simulators.
interface pins. Enter a prefix for all memory interface pins
associated with this custom variation.
Click Step 2: Constraints in IP Toolbench.
Choose the positions on the device for each of the QDRII SRAM
byte groups. To place a byte group, select the byte group in the
drop-down box at your chosen position.
1
Example Design
example_top
MegaCore Version 9.1
QDRII SRAM Controller
The floorplan matches the orientation of the Quartus II
floorplanner. The layout represents the die as viewed from
above. A byte group consists of a cq pin and a number of q
pins (the same number as the data width).
sub_system_inst
my_system_inst
Subsystem
QDRII SRAM Controller MegaCore Function User Guide
System
QDRII SRAM
Interface
QDRII SRAM
Getting Started
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