IPSRAMQDRII Altera, IPSRAMQDRII Datasheet - Page 45

• Manufacturer Part Number: IPSRAMQDRII
• Manufacturer: Altera

Specifications of IPSRAMQDRII

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Figure 3–9. Write—Burst of Four (Wide Mode)
Altera Corporation
November 2009
avl_wait_request_wr
avl_data_wr[35:0]
avl_adr_wr[19:0]
qdrii_bwsn[1:0]
avl_clock_wr
qdrii_d[17:0]
qdrii_a[19:0]
system_clk
qdrii_wpsn
avl_write
avl_clk
Bursts
Bursts are only possible on the Avalon side in the burst of two mode,
where you can transfer data every clock cycle and in bursts of four
(narrow mode). It is not possible in the burst of four (wide mode), because
it takes two QDRII SRAM clock cycles to transfer one Avalon clock cycle
of data.
Figure 3–10 on page 3–14
two write requests are sent on the Avalon interface at consecutive
addresses, the controller automatically concatenates them and transfers
them to the QDRII SRAM, if the first one is an even address. If more data
is coming in the following cycle, it is also sent straight away, without any
pause.
01020304
01020304
0001
0001
MegaCore Version 9.1
QDRII SRAM Controller MegaCore Function User Guide
shows the burst of four (narrow mode). When
0001
0001
01
02
Functional Description
00
00
03
04
04
3–13