IPSRAMQDRII Altera, IPSRAMQDRII Datasheet - Page 57

• Manufacturer Part Number: IPSRAMQDRII
• Manufacturer: Altera

Specifications of IPSRAMQDRII

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Altera Corporation
November 2009
control_wpsn
dll_delay_ctrl
capture_clock
captured_data
avl_control_a_rd
avl_control_a_wr
avl_control_bwsn
avl_control_rpsn
avl_control_wdata
avl_control_wpsn
capture_clock
captured_data
clk
reset
control_a_rd
control_a_wr
control_bwsn
control_rdata
control_rpsn
control_wdata
control_wpsn
training_done
Table 3–5. Datapath Interface Signals (Part 2 of 2)
Table 3–6. Pipeline & Resynchronization Logic Signals
Name
Name
–
5:0
–
35:0
Width
(Bits)
Table 3–6
17:0
17:0
3:0
–
35:0
–
–
35:0
–
–
17:0
17:0
3:0
35:0
–
35:0
–
–
Width
(Bits)
Direction
Input
Input
Output
Output
shows the datapath.
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Output
Output
Output
Output
Input
Direction
MegaCore Version 9.1
Write signal from the pipeline and resynchronization logic.
DLL delay control from the top-level design to shift the
nominal 90 degrees.
Capture clocks (CQ into soft logic) to the pipeline and
resynchronization logic.
Captured data—data after the IO to pipeline and
resynchronization logic.
QDRII SRAM Controller MegaCore Function User Guide
Read address from the control logic.
Write address from the control logic.
Byte enable from the control logic.
Read from the control logic.
Write data from the control logic.
Write from the control logic.
Clocks from the datapath (CQ into soft logic).
Data captured by IO from datapath.
Clock.
Reset.
Read address to datapath.
Write address to datapath.
Byte enable to datapath.
Read data after resynchronization to control logic.
Read to datapath.
Write data to datapath.
Write to datapath.
Initial training done to control logic.
Description
Description
Functional Description
CQ
by a
3–25