IPSRAMQDRII Altera, IPSRAMQDRII Datasheet - Page 63

• Manufacturer Part Number: IPSRAMQDRII
• Manufacturer: Altera

Specifications of IPSRAMQDRII

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Altera Corporation
November 2009
Number of pipeline
registers on address,
command, and data
outputs
Number of pipeline
registers on read data
Table 3–11. Pipelining Parameters
Parameter
0 to 4
0 to 4
Value
Table 3–9
length of four).
Table 3–10
Board & Controller
Table 3–11
Local bus width
Device width
Device depth
Use
Table 3–9. Local Bus Width Parameters
Table 3–10. Memory Interface Parameters
altddio
Parameter
Parameter
shows the local bus width parameter (only available with burst
You can choose 1, 2, or 3 pipeline registers between the memory
controller and the address, command, and data outputs. These
registers help to achieve the required performance at higher
frequencies.
You can choose 1, 2, or 3 pipeline registers between the memory
controller and the read data input. These registers help to achieve the
required performance at higher frequencies.
shows the pipelining parameters.
shows the memory interface parameters.
MegaCore Version 9.1
pin
QDRII SRAM Controller MegaCore Function User Guide
1 to 4
Narrow mode
or wide mode
1 to 2
On or off
Value
Value
Description
Narrow mode is twice the width of
the memory; wide mode is four
times the width of the memory.
Specifies the number of devices to
increase the width of the data bus.
Choose 2 to double the memory
space.
When turned on
generate the clock outputs. Turn off
to use dedicated PLL outputs to
generate the clocks, which is
recommended for HardCopy II
devices.
Description
Description
Functional Description
altddio
outputs
3–31