IPSRAMQDRII Altera, IPSRAMQDRII Datasheet - Page 28

• Manufacturer Part Number: IPSRAMQDRII
• Manufacturer: Altera

Specifications of IPSRAMQDRII

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Edit the PLL
Edit the PLL
2–18
QDRII SRAM Controller MegaCore Function User Guide
f
3.
4.
5.
6.
7.
8.
9.
10. Change Run for to 500 s.
11. Add the testbench files. In the File name field browse to the location
12. Click OK.
13. Click OK.
14. On the Tools menu point to EDA Simulation Tool and click Run
The IP Toolbench-generated example design includes up to two PLLs
(system PLL and fedback clock PLL), which have an input to output clock
ratio of 1:1 and a clock frequency that you entered in IP Toolbench. In
addition, IP Toolbench correctly sets all the phase offsets of all the
relevant clock outputs for your design. You can edit either PLLs’ input
clock to make it conform to your system requirements. If you re-run IP
Toolbench, it does not overwrite the system PLL, if you turn off Reset the
PLL to the default setting, so your edits are not lost.
For more information on the PLL, refer to
page
Check that the absolute path to your third-party simulator
executable is set. On the Tools menu click Options and select EDA
Tools Options.
On the Processing menu, point to Start and click Start Analysis &
Elaboration.
On the Assignments menu click Settings, expand EDA Tool
Settings and select Simulation. Select a simulator under Tool Name
and in NativeLink Settings, select Compile Test Bench and click
Test Benches.
Click New.
Enter a name for the Test bench name.
Enter the name of the automatically generated testbench, <project
name>_tb, in Test bench entity.
Enter the name of the top-level instance in Instance.
of the memory model and the testbench, <project name>_tb, click OK
and click Add.
EDA RTL Simulation.
3–26.
MegaCore Version 9.1
“PLL Configuration” on
Altera Corporation
November 2009