IPSRAMQDRII Altera, IPSRAMQDRII Datasheet - Page 56

• Manufacturer Part Number: IPSRAMQDRII
• Manufacturer: Altera

Specifications of IPSRAMQDRII

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Interfaces & Signals
3–24
QDRII SRAM Controller MegaCore Function User Guide
avl_datavalid_rd
avl_wait_request_
rd
clk
control_a_rd
control_a_wr
control_bwsn
control_rpsn
control_wdata
Table 3–3. Avalon Read Signals (Part 2 of 2)
Table 3–5. Datapath Interface Signals (Part 1 of 2)
Signal
Name
1
1
–
17:0
17:0
3:0
–
35:0
Width (Bits) Direction
Width
(Bits)
Table 3–4
Table 3–5
qdrii_a
qdrii_bwsn
qdrii_cq
qdrii_cqn
qdrii_d
qdrii_k
qdrii_kn
qdrii_q
qdrii_rpsn
qdrii_wpsn
Table 3–4. QDRII Memory Signals
Signal
Direction
Input
Input
Input
Input
Input
Input
shows the QDRII memory signals.
shows the datapath interface signals.
Output
Output
MegaCore Version 9.1
Clock.
Read address from the pipeline and resynchronization logic.
Write address from the pipeline and resynchronization logic.
Byte enable from the pipeline and resynchronization logic.
Read from the pipeline and resynchronization logic.
Write data from the pipeline and resynchronization logic.
Width (Bits) Direction
 21
72
72
Avalon read data valid—the data is sent concurrent to
the signal.
Avalon read wait—the transaction does not occur on this
cycle.
 8
 9
 9
9
9
8
8
Output
Output
Input
Input
Output
Output
Output
Input
Output
Output
Description
Address bus.
Byte enable to memory.
Free running clock from memory.
Free running clock from memory.
Data out.
Free running clock to memory.
Free running clock to memory.
and reset in the inactive state.
and reset in the inactive state.
Description
Data in from memory.
Read signal to memory. Active low
Write signal to memory. Active low
Description
Altera Corporation
November 2009