IPSRAMQDRII Altera, IPSRAMQDRII Datasheet - Page 44

• Manufacturer Part Number: IPSRAMQDRII
• Manufacturer: Altera

Specifications of IPSRAMQDRII

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Interfaces & Signals
Figure 3–8. Write—Burst of Two
3–12
QDRII SRAM Controller MegaCore Function User Guide
avl_wait_request_wr
avl_data_wr[35:0]
avl_adr_wr[19:0]
qdrii_bwsn[1:0]
avl_clock_wr
qdrii_d[17:0]
qdrii_a[19:0]
system_cl k
qdrii_wpsn
avl_write
avl_clk
Figure 3–8
away and puts it on the QDRII SRAM interface a few cycle later (the exact
timing may change). Because it takes as many Avalon clock cycles as
QDRII SRAM clock cycles to write the data, you can put write accesses
back-to-back. The write cycles have no influence on the read cycles as the
address is put on half a clock cycle.
Figure 3–9 on page 3–13
present in one clock cycle. After one Avalon write, you can transfer data
for two clock cycles on the QDRII SRAM interface. In this example, all the
data bits are valid and the byte mask is set to enable the whole transfer.
00010002
00010002
0001
0001
shows a burst of two, the controller takes the data straight
MegaCore Version 9.1
shows a burst of four (wide mode), all the data is
0001 0002
0001
0001
00
00
0002
Altera Corporation
November 2009