IPSRAMQDRII Altera, IPSRAMQDRII Datasheet - Page 30

• Manufacturer Part Number: IPSRAMQDRII
• Manufacturer: Altera

Specifications of IPSRAMQDRII

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Compile the Example Design
set_instance_assignment -name GLOBAL_SIGNAL OFF -to soft_reset_n
set_global_assignment -name OPTIMIZE_FAST_CORNER_TIMING ON
2–20
QDRII SRAM Controller MegaCore Function User Guide
f
f
For more information on the DTW, refer to the
2.
3.
If your design does not meet timing requirements, add the following lines
to you .qsf file:
If the compilation does not reach the frequency requirements, follow
these steps:
1.
2.
3.
4.
5.
To view the constraints in the Quartus II Assignment Editor, choose
Assignment Editor (Assignments menu).
1
For more information on constraints, refer to
page
b.
Choose Start Compilation (Processing menu), which runs the add
constraints scripts, compiles the example design, and performs
timing analysis.
View the Classic or TimeQuest Timing Analyzer to verify your
design meets timing.
Choose Settings (Assignments menu).
Choose Analysis and Synthesis Settings in the category list.
Select Speed in Optimization Technique.
Click OK.
Re-compile the example design by choosing Start Compilation
(Processing menu).
3–29.
Use the DDR timing wizard (DTW) to generate the required
QDRII SRAM Synopsys design constraint (SDC) TimeQuest
constraints for the design.
If you have “?” characters in the Quartus II Assignment Editor,
the Quartus II software cannot find the entity to which it is
applying the constraints, probably because of a hierarchy
mismatch. Either edit the constraints script, or enter the correct
hierarchy path in the Hierarchy tab (refer to step
page
MegaCore Version 9.1
2–6).
“Constraints” on
DTW User
Altera Corporation
November 2009
Guide.
13
on