IPSRAMQDRII Altera, IPSRAMQDRII Datasheet - Page 24

• Manufacturer Part Number: IPSRAMQDRII
• Manufacturer: Altera

Specifications of IPSRAMQDRII

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Simulate the Example Design
2–14
QDRII SRAM Controller MegaCore Function User Guide
<device name>
auk_qdrii_lib
Table 2–3. Files to Compile—VHDL Gate-Level Simulations
Library
<QUARTUS ROOTDIR>/eda/sim_lib/<device name>_atoms.vhd
<QUARTUS ROOTDIR>/eda/sim_lib/<device name>_components.vhd
<project directory>/simulation/<simulator name>/<project name>.vho
<project directory>/testbench/<project name>_tb.vhd
4.
5.
VHDL Gate-Level Simulations
For VHDL simulations with gate-level models, follow these steps:
1.
2.
3.
4.
5.
Verilog HDL IP Functional Simulations
For Verilog HDL simulations with IP functional simulation models,
follow these steps:
1.
2.
Set the Tcl variable gRTL_DELAYS to 1, which tells the testbench to
model the extra delays in the system necessary for RTL simulation
Load the testbench in your simulator with the timestep set to
picoseconds.
Create a directory in the <project directory>\testbench directory.
Launch your simulation tool inside this directory and create the
following libraries.
●
●
Compile the files in
are in VHDL93 format.
Set the Tcl variable gRTL_DELAYS to 0, which tells the testbench not
to use the insert extra delays in the system, because these are
applied inside the gate-level model.
Load the testbench in your simulator with the timestep set to
picoseconds.
Create a directory in the <project directory>\testbench directory.
Launch your simulation tool inside this directory and create the
following libraries.:
<device name>
auk_qdrii_lib
MegaCore Version 9.1
Table 2–3
Filename
into the appropriate library. The files
Altera Corporation
November 2009