IPSRAMQDRII Altera, IPSRAMQDRII Datasheet - Page 55

• Manufacturer Part Number: IPSRAMQDRII
• Manufacturer: Altera

Specifications of IPSRAMQDRII

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Altera Corporation
November 2009
avl_addr_wr
avl_byteen_wr
avl_chipselect_wr
avl_data_wr
avl_write
avl_wait_request_
wr
avl_addr_rd
avl_byteen_rd
avl_chipselect_rd
avl_read
avl_data_rd
Table 3–2. Avalon Write Signals
Table 3–3. Avalon Read Signals (Part 1 of 2)
Signal
Signal
 21
2, 4, 8, or 16
1
18, 36, 72,
144, or 288
1
1
 21
2 to 16
1
1
18, 36, 72,
144, or 288
Width (Bits) Direction
Width (Bits) Direction
Table 3–2
Table 3–3
non_dqs_capture
_clock
training_done
training_incorrec
t
training_pattern_
not_found
Table 3–1. System Signals (Part 2 of 2)
Signal
shows the Avalon write signals.
shows the Avalon read signals.
Input
Input
Input
Input
Input
Output
Input
Input
Input
Input
Output
MegaCore Version 9.1
QDRII SRAM Controller MegaCore Function User Guide
Avalon write address.
Byte enable (active low).
Device select for the write port.
Avalon data write from master.
Avalon write request.
Avalon write wait—the transaction does not occur on this
cycle.
Avalon read address.
Byte enable (active low).
Device select for the read port.
Avalon read request.
Avalon read data to master.
Input
Output
Output
Output
Direction
Non-DQS capture mode clock.
Asserted when the training of the core
is complete.
The core is nonfunctional.
Asserted when the training reaches
the maximum number of iterations but
fails to adjust the pointers.
The core is nonfunctional. The
training must find a positive edge on
the bit 0 of data. The core did not find
this edge.
Description
Description
Description
Functional Description
3–23