IPSRAMQDRII Altera, IPSRAMQDRII Datasheet - Page 43

• Manufacturer Part Number: IPSRAMQDRII
• Manufacturer: Altera

Specifications of IPSRAMQDRII

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Figure 3–7. Isolated Write—Burst of Four (Narrow Mode)
Altera Corporation
November 2009
avl_wait_request_wr
avl_data_wr[35:0]
avl_adr_wr[19:0]
qdrii_bwsn[1:0]
qdrii_d[17:0]
qdrii_a[19:0]
system_clk
qdrii_wpsn
avl_write
write_clk
f
clk
■
■
■
For more information on the Avalon interface, refer to the
Interface
Writes
This section discusses the following topics:
■
■
■
If the address is the consecutive, you can have consecutive write cycles
(refer to
into two transfers and you must pause a transfer (refer to
Pauses” on page
Isolated Write
Figure 3–7
mode). The Avalon interface receives a write request, which the
controller immediately accepts. It then transfers the write data (the exact
timing may vary) to the QDRII SRAM interface. As it receives only half
the required data for a burst of four, it masks the second part of the burst
on the QDRII SRAM interface as invalid.
00010002
00010002
Writes
Reads
Simultaneous Read & Write Timing
“Isolated Write” on page 3–11
“Bursts” on page 3–13
“Bursts with Pauses” on page 3–14
0001
0001
Specifications.
“Bursts” on page
shows an isolated write transaction on a burst of four (narrow
MegaCore Version 9.1
3–14).
QDRII SRAM Controller MegaCore Function User Guide
3–13). Non-consecutive addresses are split
0001
0001
0001 0002
00
0002
Functional Description
11
11
“Bursts with
Avalon
3–11