IPSRAMQDRII Altera, IPSRAMQDRII Datasheet - Page 59

• Manufacturer Part Number: IPSRAMQDRII
• Manufacturer: Altera

Specifications of IPSRAMQDRII

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Figure 3–20. PLL Configuration
Notes to
(1)
(2)
Altera Corporation
November 2009
clock_source
Stratix II devices only.
Non-DQS mode only.
Figure
3–20:
FPGA Device
Enhanced PLL
Example Design
IP Toolbench creates an example design that shows you how to
instantiate and connect up the QDRII SRAM controller. The example
design is a working system that can be compiled and used for both static
timing checks and board tests. It also instantiates an example PLL and
shows you how to generate the external clocks for the QDRII SRAM
device.
The example design consists of the QDRII SRAM controller, some driver
logic to issue read and write requests to the controller, and a PLL to create
the necessary clocks. The asynchronous reset, avl_resetn, drives the
reset logic, which resets the PLL and all the logic. When the PLL is locked
and avl_resetn is deasserted, the reset to the core, soft_reset_n, is
also deasserted. If the PLL lock is lost, the reset logic issues a reset.
Figure 3–21 on page 3–28
C0
C1
capture_clock
non_dqs_
clk
write_clk
MegaCore Version 9.1
QDRII SRAM
Controller
QDRII SRAM Controller MegaCore Function User Guide
Fed-Back Clock
Stratix II DLL
PLL (Note 2)
shows the testbench and the example design.
Optional
(Note 1)
altddio
altddio
qdrii_k_n
qdrii_k
qdrii_cq
Functional Description
QDRII SRAM
3–27