IPSRAMQDRII Altera, IPSRAMQDRII Datasheet - Page 64

• Manufacturer Part Number: IPSRAMQDRII
• Manufacturer: Altera

Specifications of IPSRAMQDRII

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Parameters
3–32
QDRII SRAM Controller MegaCore Function User Guide
DQS mode
Use migratable byte
groups
Pin loading on data
pins
Pin loading on FPGA
address and
command pins
Pin loading on FPGA
clock pins
Table 3–13. Capture Modes
Table 3–14. Pin Loading Parameters
Parameter
Parameter
On or off
On or off
Any
Any
Any
Range (pF)
Value
Table 3–12
Table 3–13
Table 3–14
Manual read latency
setting
Set latency to clock cycle
Table 3–12. Read Latency Options
Parameter
Turn on for DQS capture mode (Stratix II devices only). The controller
is in non-DQS mode only for Stratix devices.
When turned on, you can migrate the design to a migration device
(Stratix II devices only). When turned off the wizard allows much
greater flexibility in the placement of byte groups.
Enter the pin loading to match your board and memory devices.
Enter the pin loading to match your board and memory devices.
Enter the pin loading to match your board and memory devices.
shows the read latency options.
shows the capture modes.
shows the pin loading parameters.
MegaCore Version 9.1
On or off
–2 < current
clock cycle <
+4
Value
Description
Description
Turn on if you want to choose the
latency clock cycle.
Choose the latency clock cycle. For
example, if the default is 13, you can
choose any value from 11 to 17.
However, Altera recommends that
you do not alter this parameter.
Description
Altera Corporation
November 2009