IPSRAMQDRII Altera, IPSRAMQDRII Datasheet - Page 19

no-image

IPSRAMQDRII

Manufacturer Part Number
IPSRAMQDRII
Description
Manufacturer
Altera
Datasheet

Specifications of IPSRAMQDRII

Lead Free Status / RoHS Status
Supplier Unconfirmed
Altera Corporation
November 2009
<variation name>.bsf
<variation name>.html
<variation name>.vhd, or .v
<variation name>_bb.v
<variation name>_auk_qdrii_sram.vhd or .v
<variation
name>_auk_qdrii_sram_addr_cmd_reg.vhd or .v
<variation
name>_auk_qdrii_sram_avalon_controller_ipfs_
wrap.vhd or .v
<variation
name>_auk_qdrii_sram_avalon_controller_ipfs_
wrap.vho or .vo
<variation
name>_auk_qdrii_sram_capture_group_wrapper.
vhd or .v
<variation name>_auk_qdrii_sram_clk_gen.vhd or
.v
<variation
name>_auk_qdrii_sram_cq_cqn_group.vhd or .v
<variation name>_auk_qdrii_sram_datapath.vhd
or .v
<variation name>_auk_qdrii_sram_dll.vhd or .v
<variation
name>_auk_qdrii_sram_example_driver
.vhd or .v
<variation
name>_auk_qdrii_sram_read_group.vhd or .v
Table 2–1. Generated Files (Part 1 of 2) (1),
Filename
Table 2–1
project directory. The names and types of files specified in the IP
Toolbench report vary based on whether you created your design with
VHDL or Verilog HDL
describes the generated files and other files that may be in your
MegaCore Version 9.1
(2)
QDRII SRAM Controller MegaCore Function User Guide
&
Quartus II symbol file for the MegaCore function
variation. You can use this file in the Quartus II block
diagram editor.
MegaCore function report file.
A MegaCore function variation file, which defines a
VHDL or Verilog HDL top-level description of the custom
MegaCore function. Instantiate the entity defined by this
file inside of your design. Include this file when compiling
your design in the Quartus II software.
Verilog HDL black-box file for the MegaCore function
variation. Use this file when using a third-party EDA tool
to synthesize your design.
File that instantiates the control logic and the datapath.
The address and command output registers.
File that instantiates the controller.
VHDL or Verilog HDL IP functional simulation model.
File that contains all the capture group modules (CQ and
CQN group modules and read capture registers).
The clock output generators.
The CQ and CQN module.
Datapath.
DLL.
The example driver.
The read capture registers.
(3)
Description
Getting Started
2–9

Related parts for IPSRAMQDRII