IPSRAMQDRII Altera, IPSRAMQDRII Datasheet - Page 60

• Manufacturer Part Number: IPSRAMQDRII
• Manufacturer: Altera

Specifications of IPSRAMQDRII

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Device-Level Configuration
Figure 3–21. Testbench & Example Design
3–28
QDRII SRAM Controller MegaCore Function User Guide
test_complete
ref_clk
pnf
Example Driver
Table 3–7
and the testbench.
The example driver is a self-checking test generator for the QDRII SRAM
controller. It uses a state machine to write data patterns to all memory
banks. It then reads back the data and checks that the data matches. If any
read data fails the comparison, the fail output transitions high for one
cycle and the fail permanent output transitions high and stays high.
The data patterns used are generated using an 8-bit counter per byte, with
each counter having a different initialization seed.
Notes to
(1)
(2)
<top-level name>_tb.v or .vhd
<top-level name>.vhd or .v
qdrii_pll_stratixii.vhd
<variation name>_example_driver.v
or .vhd
<variation name> .v or .vhd
PLL
Table 3–7. Example Design & Testbench Files
<top-level name> is the name of the Quartus II project top-level entity.
<variation name> is the is the name you give to the controller you create with the
Megawizard.
(2)
Table
describes the files that are associated with the example design
MegaCore Version 9.1
Example Design
Filename
3–7:
QDRII SRAM Controller
Testbench
(1)
(2)
(1)
DLL
Testbench for the example design.
Example design.
Example PLL, which you should
configure to match your frequency.
Example driver.
QDRII SRAM controller.
Description
Altera Corporation
QDRII SRAM
November 2009
Model