IPSRAMQDRII Altera, IPSRAMQDRII Datasheet - Page 51

• Manufacturer Part Number: IPSRAMQDRII
• Manufacturer: Altera

Specifications of IPSRAMQDRII

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Figure 3–16. Burst with Non-Consecutive Address—Burst of Four (Narrow Mode)
Altera Corporation
November 2009
avl_data_read_valid
avl_wait_request_rd
avl_data_rd[19:0]
avl_data_rd[17:0]
qdrii_a[19:0]
qdrii_q[17:0]
qdrii_rpsn
avl_read
qdrii_cqn
qdrii_cq
qdrii_k
avl_clk
0001 1220
Simultaneous Read & Write Timing
This section discusses the following topics:
■
■
■
The QDRII SRAM protocol allows simultaneous reads and writes to the
memory. As the address bus is shared between the read and write, if a
concurrent read and write occurs, some arbitration may be necessary.
Burst of Four (Narrow Mode)
For a burst of four, you cannot send a read and a write request during the
same clock cycle. Because it takes two clock cycle per transfer, you can
alternate reads and writes every other cycle. Thus you lose no bandwidth
apart from an initial one clock cycle on either the read or the write.
When a read and a write arrive at the same time, the write takes priority
over the read. For a continuous read and write, there is a one off pause on
the read side, refer to
1221
“Burst of Four (Narrow Mode)” on page 3–19
“Burst of Two” on page 3–20
“Burst of Four (Wide Mode)” on page 3–21
MegaCore Version 9.1
0001
QDRII SRAM Controller MegaCore Function User Guide
Figure 3–17 on page
1220
01 02 xx xx 31 32 33 34
3–20.
34
Functional Description
0102
3132 3334
3334
3–19