IPSRAMQDRII Altera, IPSRAMQDRII Datasheet - Page 47

• Manufacturer Part Number: IPSRAMQDRII
• Manufacturer: Altera

Specifications of IPSRAMQDRII

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Figure 3–11. Write Burst with Pause—Burst of Four (Narrow Mode)
Altera Corporation
November 2009
qdrii_bwsn[1:0]
avl_clock_wr
avl_addr_wr
qdrii_d[17:0]
qdrii_a[19:0]
avl_data_wr
system_clk
request_wr
qdrii_wpsn
avl_wait_
avl_clk
[19:0]
[35:0]
write
00010002 11031104
0001
For a burst of four (wide mode), you cannot transfer more than one write
request every other cycle, because it takes two cycles on the QDRII SRAM
side to send the data. Therefore, if two consecutive writes arrive, the
controller pauses the second one for one clock cycle.
Reads
This section discusses the following topics:
■
■
■
Isolated Read
Figure 3–12 on page 3–16
interface for a burst of four. The Avalon read FSM issues a latent read and
transfers the data back at a later stage, which frees the Avalon interface.
The controller transfers the read to the QDRII SRAM. A few cycles later
(timing is not accurate), the data arrives, in synchronization with the cq
and cqN clocks. Even though only one set of data was requested, the
memory send two sets of data. The controller captures and
resynchronizes the data onto the system clock and it appears on the
Avalon interface a few cycles later. The controller asserts
avl_data_read_valid with the data to validate the data cycle.
1122
“Isolated Read” on page 3–15
“Burst” on page 3–17
“Bursts with Pauses” on page 3–18
11051106
11051106
MegaCore Version 9.1
1123
QDRII SRAM Controller MegaCore Function User Guide
shows a read request from the Avalon read
0001
0001 0002
00
1122
11
Functional Description
1103 1104 1105 1106
00
00
1106
3–15