RPIXP2850BB Intel, RPIXP2850BB Datasheet
RPIXP2850BB
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RPIXP2850BB Summary of contents
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... Intel IXP28XX Network Processors Hardware Design Guide August 2005 Order Number: 309192-002US ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. ...
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... System Overview................................................................................................................11 1.2 In This Guide ......................................................................................................................13 1.2.1 Typographical Conventions ...................................................................................14 1.2.2 Acronyms and Terminology ...................................................................................14 1.3 Related Documentation ......................................................................................................16 1.4 Contacting Intel® ................................................................................................................16 2 Power Ratings and Requirements .................................................................................................17 2.1 Power Ratings ....................................................................................................................17 2.2 Supply Voltage Power-up Sequence ..................................................................................24 2.2.1 Sequence for 1.4 / 1.0 GHz Devices .....................................................................24 2.2.2 Sequence for 650 MHz Devices ............................................................................24 2 ...
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... IXP28XX Network Processor Contents 4.4 QDR SRAM Interface ......................................................................................................... 57 4.4.1 Using x9 Versus x18 QDR SRAM Parts ................................................................ 58 4.4.1.1 Examples of the QDR Interface ............................................................. 60 4.4.2 Signal Groups ........................................................................................................ 62 4.4.3 QDR Signal Mapping ............................................................................................. 62 4.4.4 ClamShell Configuration of SRAMs....................................................................... 63 4.4.5 QDR SRAM Input/Output Timing Specifications.................................................... 64 4.4.5.1 IXP2800 Input Timing ............................................................................ 64 4 ...
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... Network Processor Controller Escape Routing - Layer 6 ...........................................................42 13 Network Processor Controller Escape Routing - Layer 13 .........................................................43 14 Network Processor Controller Escape Routing - SCK/CMD Signals Routed on Layer 12 .........44 15 Network Processor Controller Escape Routing - SCK/CMD Signals Routed on Layer 16 .........45 16 Three-Channel Controller to HCD NexMod* RDRAM Routing - Layer 4....................................46 17 Three-Channel Controller to HCD NexMod* RDRAM Routing - Layer 6 ...
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... Topology 2 - Two Unique PCBs with Signal Loopback Through Connectors .......................... 107 63 PCI Subsystem ......................................................................................................................... 112 64 PPCI Address/Data Signal Topology........................................................................................ 113 65 PPCI Clock Signals Topology................................................................................................... 114 66 Address/Data Signals with IDSEL Topology (Showing Only the Ingress Intel® IXP28XX Network Processor) ........................................................................................ 115 67 SPCI Address/Data Signal Topology........................................................................................ 116 68 SPCI Clock Signals Topology................................................................................................... 117 6 ...
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... Intel® IXP2800 Network Processor Package Marking .............................................................148 90 Intel® IXP2850 Network Processor Package Marking .............................................................148 91 Intel® IXP2800 or Intel® IXP2850 Network Processor Package Ball Grid Array .....................149 92 Intel® IXP2800 or Intel® IXP2850 Network Processor Package Side View.............................149 93 Intel® ...
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... SPCI Address/Data Signals with IDSEL Group Guidelines ...................................................... 119 45 cPCI Signal Group Guidelines .................................................................................................. 120 46 Package Trace Lengths for PCI Signals................................................................................... 124 47 Signal Description..................................................................................................................... 130 48 Slowport Control Signals Routing Guidelines ........................................................................... 131 49 Slowport Clock Signals Guideline............................................................................................. 132 50 Slowport Address/Data Routing Guidelines ............................................................................. 133 51 Intel® IXP2800 or IXP2850 Network Processor Package Dimensions .................................... 150 8 ...
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... Revision History Date Revision August 2005 002 Updates to Chapter 4 QDR SRAM. December 2004 001 Initial release IXP28XX Network Processor Revision History Description 9 ...
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... IXP28XX Network Processor Revision History 10 ...
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... Microengine architecture that includes a multi-threaded distribution cache architecture that enables pipeline features in software. In addition to the standard feature set available with the Intel® IXP2800 Network Processor, the Intel® IXP2850 Network Processor integrates functionality for secure network traffic at 10 Gbytes/sec ...
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... Hardware support for Linked List and Ring operations • Atomic bit operations • Atomic arithmetic support ® • Addressable from Intel XScale core, Microengines, and PCI • Two unidirectional 16-bit Low-Voltage Differential Signaling (LVDS) data interfaces • 500 MHz per channel • ...
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... Fabric Memory (MSF) Hash Crypto Crypto Unit 0 1 Intel® IXP2850 Network Processor Only 1.2 In This Guide This document comprises the following chapters and appendixes that describe the IXP28XX network processor: • Chapter 2, “Power Ratings and Requirements,” operating voltages and temperatures. ...
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... IXP28XX Network Processor Introduction 1.2.1 Typographical Conventions This guide contains the following text and typography conventions: Table 2. Guide Conventions Convention Italics bold monospace monospace bold table of contents table of figures table of tables > 1.2.2 Acronyms and Terminology Table 3 defines the acronyms and terminology that are used throughout this document. ...
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... Secondary PCI, a 32-bit bus operating at 33 MHz Interface for packet and cell transfer between a physical layer (PHY) device and a link layer device (the IXP28XX network processor), for aggregate bandwidths of OC-192 ATM and Packet over SONET/SDH (POS), as well as 10 Gb/s Ethernet applications. ...
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... Refer to the following documents or models for more information. All Intel-issued documentation revision numbers are subject to change, and the latest revision should be used. The specific revision numbers referenced should be used for all documents not released by Intel. Contact your field representative for information on obtaining Intel-issued documentation. ...
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... Power Ratings and Requirements The following sections describe power ratings and requirements for the Intel IXP2850 Network Processors. 2.1 Power Ratings Operation beyond the functional operating temperature range (see and extended exposure beyond this range may affect reliability. functional operating voltage ranges; ...
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... IXP2800 - Bn IXP2800 - Bn IXP2800 - Bn IXP2850 - Bn IXP2850 - Bn IXP2850 - Bn 1. The maximum power parameters represent the worst-case power consumption as measured by running the Intel packet over SONET (POS) reference design processing minimum-size packets (49 bytes) running at full OC-192 line rate. 2. Total power refers to B0 and B1. 18 ...
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... SPI-4 reference should be derived from VCC25V so that they track fluctuations in VCC25V. 5. The tolerance on the PCI supply is tighter than specified in the PCI Local Bus Specification, Version 2.2*. Hardware Design Guide IXP28XX Network Processor Power Ratings and Requirements Description Voltage (V) Core power supply 1 ...
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... IXP28XX Network Processor Power Ratings and Requirements Table 8. Functional Operating Voltage Range – 650 MHz Interface Supply Name VCC Core VSS VCC_PLL VSS VCC_CLK Clock/PLL VREFHI_CLK VREFLO_CLK VCC25V VCCA_FC SPI-4/CSIX/F VCCA_SPI4 LOW VREFHI VREFLO GPIO VCC33 PCI VCC33_PCI VDDQ PAS0_VCCA PAS1_VCCA ...
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... VCC33_PCI VREF_QDR0 VREF_QDR1 0.75 VREF_QDR2 VREF_QDR3 VREFLO_CLK 1.0 V VREF_LO VREFHI_CLK VREFHI PAR0_PADVREFA PAR0_PADVREFB 1.4 V PAR1_PADVREFA PAR1_PADVREFB PAR2_PADVREFA PAR2_PADVREFB IXP28XX Network Processor Power Ratings and Requirements 1 Max Power IXP2800 IXP2850 25.5 W 28.0 W 1.0 W 1.0 W 2.0 W 2.0 W 0.5 W 0.5 W 1.8 W 1.8 W 0.7 W 0.7 W < ...
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... IXP28XX Network Processor Power Ratings and Requirements Table 10. Example Power by Supply – 1.0 GHz Type Power Supplies Voltage References 1. Power specified is in the total for all the supplies/references in each group. 22 Group Names VCC VCCR 1.3 V logic VCCRA VCC_FUSE VCC_PLL VCCA_FC VCCA_SPI4 1 ...
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... VCC33_PCI VREF_QDR0 VREF_QDR1 0.75 V VREF_QDR2 VREF_QDR3 VREFLO_CLK 1.0 V VREF_LO VREFHI_CLK VREFHI PAR0_PADVREFA PAR0_PADVREFB 1.4 V PAR1_PADVREFA PAR1_PADVREFB PAR2_PADVREFA PAR2_PADVREFB IXP28XX Network Processor Power Ratings and Requirements 1 Max Power IXP2800 IXP2850 10.4 W 11.8 W 1.0 W 1.0 W 1.9 W 1.9 W 0.4 W 0.4 W 1.7 W 1.7 W 0.7 W 0.7 W < ...
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... Power Ratings and Requirements 2.2 Supply Voltage Power-up Sequence Caution: The IXP28XX network processors each have a prescribed supply voltage bring-up sequence that must be followed, or permanent damage to the device may result. This section provides the bring- up sequence for 1.4 /1.0 GHz devices 2 ...
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... A 1uF 0402 capacitor is now available from AVX* which can be substituted for the 0.22 uF capacitor. This will provide better regulation stability during the power-on transient event. Refer to Section 2.5 Hardware Design Guide 2.2.3.1. The IXDP2800 decoupling design implements a via-sharing for details of the power-on transient event. IXP28XX Network Processor Power Ratings and Requirements 25 ...
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... Figure 3 shows an example filter design that can be used to derive the power for the analog and DLL power supplies for the IXP2800 or IXP2850 network processor. For L1, a 10-Ω ferrite bead with a DCR of less than 0.1 Ω should be used. For C1 µF capacitor should be used and each analog V The IXDP2800 Advanced Development Platform uses analog power for all PLL/DL pins ...
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... Section 2.4.2, “Power-up Sequence” 2.4.1 Subsystem Block Diagram Figure block diagram for the IXDP2800 Advanced Development Platform power supply subsystem. Hardware Design Guide IXP28XX Network Processor Power Ratings and Requirements Ω 0.1 µ µF 0.1 µF 0.1 µF .01 µF .01 µ ...
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... Linear) (Intel ® IXP2800 Network Processor, QDR, RDRAM) (16A max) 2.5V (1 FET) (Intel ® IXP2800 Network Processor, Logic, I/O) (8A max) 1.0V (reference) ® ® (Intel IXP2800 (Intel IXP2800 Network Processor SPI, Rambus*) Clk, SPI) B3429-01 Hardware Design Guide ...
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... IXDP2800 Advanced Development Platform power supply. Figure 5. IXDP2800 Advanced Development Platform Power-up Sequence .75 V 1 1.8 V Ingress 1.8 V Egress 2.5 V 3.3 V Supply Time Hardware Design Guide IXP28XX Network Processor Power Ratings and Requirements 150 ms 300 ms 450 ms B3430-01 29 ...
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... I_lkg 6 tclks 4. Figure 6) represents a 9.29-W step (i.e., the transient step) Figure 6) represents a 13.515-W step (i.e., the transient ® Intel IXP2800 Network Processor di/dt Stimulus (B Step Power-Up Condition @ 1.365 V with Microengine Reset) Icc_max tr2 I_mid 9 tclks 6. REF_CLK cycles or ~0.67 µs @ 100 MHz ) ...
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... Droop Analysis Results An exhaustive droop analysis was performed using an Intel system validation platform. The goal of analysis was to correlate the measured power-on di/dt with the theoretical design values. A detailed model of the system board, power delivery circuit and package were developed and simulated using the theoretical di/dt transient events to predict the voltage droop measured at the pins of the device ...
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... IXP28XX Network Processor Power Ratings and Requirements 32 Hardware Design Guide ...
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... It is also possible (for system cost and area savings) to have channels 0 and 1 populated with channel 2 empty, or channel 0 populated with channels 1 and 2 empty. Reads and writes to RDRAM are generated by Microengines, Intel XScale (external Bus Masters and DMA Channels). The controllers also do refresh and calibration cycles to the RDRAMs, transparently to software. ...
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... IXP28XX Network Processor RDRAM The multi-tiered NexMod* module contains all of the circuitry for an entire Rambus* channel in a single module. The NexMod* module can be attached either to the main board with pin grid array (PGA) connectors or soldered with ball grid array (BGA) technology. The module incorporates termination resistors, the Direct Rambus* Clock Generator (DRCG), and a Voltage Regulator Module (VRM) on the same modular subsystem as the memory chips ...
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... Using 512- Mbyte part Mbyte part 768 Mbytes 1.5 Gbytes • Vendors: Elpida*, Samsung* • Vendor: Samsung*. 384 Mbytes 768 Mbytes • Rambus* is working with vendors to establish a standard. 3.7. Section 3.7 IXP28XX Network Processor RDRAM Comments must be adjusted to reflect the Section 3.7. 35 ...
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... Unused Channel Guidelines It is not a requirement to implement all three RDRAM channels available on the IXP28XX network processor. However, if only a single channel is implemented it MUST be channel 0. If two channels are implemented then they MUST be channels 0 and 1. No other channel combinations are supported in these modes. ...
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... NexMod* modules. Because each channel can have a separate power source for V and V TERM supply for the IXP28XX network processor, is common to all three channels as shown in the following requirement must be satisfied by the power delivery design: • The system designer must ensure that V — ...
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... Each channel’s V example of this implementation is shown in • The RDRAM V Figure 8. Common V CCR_IO ® Intel IXP2800 Network Processor 3.3 IXP28XX Network Processor Rambus* Controller Footprint and Via Placement The following figures illustrate the IXP28XX network processor Rambus* controller footprint and via placement: • ...
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... Figure 9. Rambus* Controller Footprint and Via Placement Showing Alternating Dogbone Orientation Hardware Design Guide IXP28XX Network Processor RDRAM 39 ...
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... IXP28XX Network Processor RDRAM Figure 10 illustrates the IXP28XX network processor Rambus* controller footprint and via placement, showing an exploded view of checkerboard detail. Figure 10. Rambus* Controller Footprint and Via Placement Showing Exploded View of Checkerboard Detail 40 Hardware Design Guide ...
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... Layer 12” • Figure 15, “Network Processor Controller Escape Routing - SCK/CMD Signals Routed on Layer 16” Figure 11 illustrates layer 4 of the IXP28XX network processor controller escape routing, using 28-Ω, 11-mil-wide traces. Figure 11. Network Processor Controller Escape Routing - Layer 4 Hardware Design Guide IXP28XX Network Processor ...
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... IXP28XX Network Processor RDRAM Figure 12 illustrates layer 6 of the IXP28XX network processor controller escape routing, using 28-Ω, 11-mil-wide traces. Figure 12. Network Processor Controller Escape Routing - Layer 6 42 Hardware Design Guide ...
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... Figure 13 illustrates layer 13 of the IXP28XX network processor controller escape routing, using 28-Ω, 11-mil-wide traces. Figure 13. Network Processor Controller Escape Routing - Layer 13 Hardware Design Guide IXP28XX Network Processor RDRAM 43 ...
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... IXP28XX Network Processor RDRAM Figure 14 illustrates IXP28XX network processor controller escape routing on layer 12, with SCK/CMD signals, using 28-Ω, 11-mil-wide traces. Figure 14. Network Processor Controller Escape Routing - SCK/CMD Signals Routed on Layer 12 44 Hardware Design Guide ...
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... Figure 15 illustrates IXP28XX network processor controller escape routing on layer 16, with SCK/CMD signals, using 28-Ω, 11-mil-wide traces. Figure 15. Network Processor Controller Escape Routing - SCK/CMD Signals Routed on Layer 16 Hardware Design Guide IXP28XX Network Processor RDRAM 45 ...
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... IXP28XX Network Processor Three-Channel Controller to HCD NexMod* RDRAM Routing The following figures illustrate routing with the IXP28XX network processor’s three-channel controller to HCD NexMod* RDRAM as implemented on the IXMB2800 development system. • Figure 16, “Three-Channel Controller to HCD NexMod* RDRAM Routing - Layer 4” ...
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... Figure 17. Three-Channel Controller to HCD NexMod* RDRAM Routing - Layer 6 Hardware Design Guide IXP28XX Network Processor RDRAM 47 ...
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... IXP28XX Network Processor RDRAM Figure 18. Three-Channel Controller to HCD NexMod* RDRAM Routing - Layer 13 Figure 19. Three-Channel Controller to HCD NexMod* RDRAM Routing - SCK/CMD Layer 12 48 Hardware Design Guide ...
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... IXP28XX network processor short channel routing example Note: The layout example depicted in been validated. Figure 20. IXP28XX Network Processor Short Channel Routing Hardware Design Guide IXP28XX Network Processor Figure 20 was implemented only as a routing study and has not RDRAM Terminations RDRAMs ® Intel IXP28XX Network Processor 49 ...
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... IXP28XX Network Processor RDRAM 3.7 Package Trace Lengths for RDRAM Signals Table 13 provides package trace lengths for RDRAM signals, listed by decreasing lengths in a given logical grouping. The flight time on the package substrate is 154ps/in which differs from the flight delay of standard FR4, typical 180ps/in result the package routing lengths in compensate for the difference in flight delay between the package and the PCB ...
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... RDR1_RQ[6] 7.645 0.301 RDR1_DQB[3] 7.565 0.298 RDR1_DQA[3] 7.273 0.286 RDR1_DQB[0] 6.813 0.268 RDR1_SIO 6.608 0.260 RDR1_RQ[4] 6.421 0.253 IXP28XX Network Processor RDRAM Metric English Signal Units Units (mm) (in) RDR2_RQ[3] 11.952 0.471 RDR2_DQB[6] 11.63 0.458 RDR2_DQB[2] 11.486 0.452 RDR2_DQB[0] 11.046 ...
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... IXP28XX Network Processor RDRAM 52 Hardware Design Guide ...
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... QDR synchronous static RAM (SRAM) and/or a coprocessor that adheres to QDR signaling. Any or all controllers can be left unpopulated if the application does not need to use them. SRAM is accessible by the Microengines, the Intel XScale core, and the PCI Unit (external bus masters and DMA). ...
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... The controller drives out a pair of K clocks (K and K#), and a pair of C clocks (C and C#). The C and C# clocks externally return to the controller for reading data. diagram of the clocking scheme for a QDR interface driving four SRAM chips. Figure 21. Clocking Scheme for a QDR Interface Driving Four SRAMs Intel® IXP2800 Network Processor 4.2.1 SRAM Controller Configurations Each channel has enough address pins (24) to support Mbytes of SRAM ...
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... Number of SRAMs on Channel Mbytes 4 Mbytes 5 Mbytes 6 Mbytes 8 Mbytes 10 Mbytes 12 Mbytes 16 Mbytes 20 Mbytes 24 Mbytes 32 Mbytes 64 Mbytes IXP28XX Network Processor QDR SRAM Total Number of Addresses Used Port-select Pairs as Port-enables Available 23:22, 21:20 4 23:22, 21:20 4 23:22, 21:20 4 23:22 3 23:22 3 None 2 None 1 RPE[2]/WPE[2] ...
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... IXP28XX Network Processor QDR SRAM Table 16. Total Memory per Channel (Sheet SRAM Size Mbytes 32 Mbytes 16M Mbytes 64 Mbytes 32M Mbytes 56 Number of SRAMs on Channel Mbytes 64 Mbytes Hardware Design Guide ...
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... QDRII-synchronous static RAM (QDRII SRAM). There may also be – in addition replacement for the pipelined QDR SRAM – a coprocessor with QDR signaling capability. Hardware Design Guide K/K#0 CIN/CIN#0 D[17:0] SA[21:0] BW[1:0] ® Intel IXP2800 QDR W#0/R#0 Channe l W#/R#1 Not Used ...
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... During the DATA-WRITE cycle or in the ADDRESS net, the IXP28XX network processor sends data to all of the SRAMs and thus, there are no hanging stubs that would cause severe reflections. ...
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... Intel ® IXP2800 Receiver READ Topology Using Four x18 SRAM Parts ® Intel IXP2800 Receiver B On-die Termination 50 ® Intel IXP2800 Receiver B On-die Termination 50 READ Topology Using Two x9 SRAM Parts IXP28XX Network Processor QDR SRAM Stub Top SRAM Stub ottom SRAM Stub ...
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... Figure 25, “Ingress IXP28XX Network Processor QDR Modular Channel Depth-Expanded QDR Interface” • Figure 26, “Ingress IXP2800 Network Processor QDR Modular Channel, Four-Load QDR Interface” Figure 24. IXP2800 Width-Expanded QDR Interface gress and Ingress Intel IXP2800 ® Platform QDR Channel QDRn_D_H[17..9] QDRn_Q_H[17..9] QDRn_D_H[8..0] QDRn_Q_H[8 ...
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... QDRn_D_H[17..9] QDRn_Q_H[17..9] QDRn_A[23..0] QDRn_ WS_L[1:0] QDRn_RPS_L[1:0] QDRn_WPS_L[1:0] QDRn_K_H/L[1:0] QDRn_K_H/L[1:0] QDRn_C_H/L[1] QDRn_CIN_H/L[1] Figure 26. Ingress IXP2800 Network Processor QDR Modular Channel, Four-Load QDR Interface gress and Ingress Intel ® IXP2800 Platform QDR Channel QDRn_D_H[17..9] QDRn_Q_H[17..9] QDRn_D_H[8..0] QDRn_Q_H[8..0] QDRn_ WS_L QDRn_A[23..0] QDRn_RPS_L[1] QDRn_WPS_L[1] QDRn_RPS_L[0] ...
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... IXP28XX Network Processor QDR SRAM 4.4.2 Signal Groups The QDR interface has six groups of signals. These are the K-Clocks, the C-Clocks, Address, Data-OUT or WRITE, Data-IN or READ, and Control. The Control group has three signals, the WRITE PORT ENABLE Active Low, the READ PORT ENABLE Active Low, and the BYTE WRITE ENABLE Active Low ...
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... DDQ DDQ = V DD_Core DD_Core – 1.8 V =250Ω =250Ω – GND =0.75 – V =0.75 ref ref IXP28XX Network Processor QDR SRAM Bottom SRAM 4 Termination (2Mx9) V =0. On-die at Q[7:0] IXP28XX Receiver On-die at Q[8] IXP28XX Receiver – – – – D[7:0] PU50Ω ...
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... ADDRESS, WRITE, and CONTROL operations. The setup-and-hold time requirements of the receiver (QDR SRAM) side needed for these operations is described in the specification sheet of the SRAM provided by the SRAM manufacturer. For further information regarding IXP2800 output timing, refer to the Intel IXP2850 Network Processors Datasheet. 4.4.6 QDR Signal Group Package Trace Length In order to obtain the best timing margin, trace length-match all signals to within ± ...
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... SRAM device. This allows the control and data signals to reach the pins of the SRAM and the IXP28XX network processor (for read) at the same time. In the case of read data being returned to the IXP28XX network processor this makes it easy to find a common data valid window for all signals to be captured by the controller ...
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... QDR Address Signals — Balanced T-Topology alanced T-Topology Intel ® IXP2800 Driver Address Pins A1 - A18 Figure 28. QDR Address Routing — T-Topology with Daisy-Chain Branches T-Topology with Daisy-Chained ranches Intel ® IXP2800 Driver Address Pins A0, A19-A21 Table 19 provides routing guidelines for the QDR address signal group 0.75V TT ...
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... QDR address signal trace width/spacing. Figure 29. QDR Address Signal Trace Width/Spacing Routing T d2 Other T signal Signals T d1 Hardware Design Guide IXP28XX Network Processor Routing Guideline Address Balanced-T topology Ground 34 Ω ±5% 60 Ω ±5% 35 Ω ±1% 10 mils 3.5 mils mils Isolation from all other signals 25mils. ...
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... QDR SRAM D (Data Out). Figure 30. D (Data Out) Routing Topology Daisy-Chained Data-Out ( D16) and Parity-Out (D8, D17) Signals ® Intel IXP2800 Driver Data-Out, Parity-Out Table 21 provides routing guidelines for the QDR D signal group. 68 Trace Trace Trace ...
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... DATA Signal Prepreg POWER or GND Plane Trace Trace Trace Thickness Thickness Width (W) Spacing (Tsignal) (TD1) [mils] (S) [mils] [mils] [mils IXP28XX Network Processor QDR SRAM Routing Guideline DATA Signal D1 B3992-01 Spacing D1 D2 between Thickness Er(D1) Er(D2) signal (Td2) groups [mils] [mils] 5 ...
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... QDR SRAM Q (Data In) topology. Figure 32. Q (Data In) Routing Topology T-Topology Data-In ( Q16), Parity-In (Q8, Q17) Signals ® Intel IXP2800 Receiver Data-in, Parity-in On-Die Termination Table 23 provides routing guidelines for the QDR Q (Data In) signal group. Table 23. QDR Q (Data In) Signal Group Routing Guidelines ...
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... DATA Signal Prepreg POWER or GND Plane Trace Trace Trace Thickness Thickness Width (W) Spacing (Tsignal) (TD1) [mils] (S) [mils] [mils] [mils IXP28XX Network Processor QDR SRAM DATA Signal D1 B3992-01 Spacing D1 D2 between Thickness Er(D1) Er(D2) signal (Td2) groups [mils] [mils] 5 ...
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... IXP28XX Network Processor QDR SRAM Figure 34. QDR K and K# Routing Topology K-Clock Signals K, K# Intel IXP2800 QDR Driver K, K# Clks Table 25 provides routing guidelines for the QDR K and K# signal groups. Table 25. QDR K and K# Signal Group Routing Guidelines Parameter Signal Group Topology Reference Plane ...
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... POWER or GND Plane Trace Trace Trace Thickness Thickness Width (W) Spacing (Tsignal) (TD1) [mils] (S) [mils] [mils] [mils D-Pkg-trace-length + D-trunk-length + 500 mil Address-Pkg-trace-length + Address-trunk-length + 900 mil IXP28XX Network Processor QDR SRAM Clk Signal D1 3994-01 Spacing D1 D2 between Thickness Er(D1) Er(D2) signal (Td2) groups ...
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... QDR C, C#, CIN, and CIN# Routing Topology C-Clk signal C, C# and CIN, CIN# Intel IXP2800 Driver Cout - Clock C, C# Intel IXP2800 Receiver Cin - Clock CIN, CIN# On-Die Termination Table 27 provides routing guidelines for the QDR C, C#, CIN, and CIN# signal groups. ...
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... K, C Clk Signal Prepreg POWER or GND Plane Trace Trace Trace Thickness Thickness Width (W) Spacing (Tsignal) (TD1) [mils] (S) [mils] [mils] [mils Q-trace-length IXP28XX Network Processor QDR SRAM Routing Guideline Clk Signal D1 3994-01 Spacing D1 D2 between Thickness Er(D1) Er(D2) signal (Td2) groups [mils] [mils] 5 ...
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... IXP28XX Network Processor QDR SRAM 4.5.7 QDR SRAM RPE#, WPE#, BWE# Control Topologies There are three types of control signals, and each is active low: Write Port Enable (WPE#), Read Port Enable (RPE#), and Byte Write Enable (BWE#). These signals have to be carefully connected, depending on how the four SRAMs are configured ...
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... CONTROL Signal Prepreg POWER or GND Plane Trace Trace Trace Thickness Thickness Width (W) Spacing (Tsignal) (TD1) [mils] (S) [mils] [mils] [mils IXP28XX Network Processor QDR SRAM Routing Guideline CONTROL Signal D1 3995-01 Spacing D1 D2 between Thickness Er(D1) Er(D2) signal (Td2) groups [mils] [mils] 5 ...
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... IXP28XX Network Processor QDR SRAM Figure 40. QDR Control BWE# Signals Routing Topology Daisy-Chained Control Signals WE#0, WE#1 Pins Intel ® IXP2800 Driver WE# Table 31 provides routing guidelines for the QDR control BWE# signal group. Table 31. QDR Control BWE# Signal Group Routing Guidelines ...
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... Generation REF generation is to derive the 0.75-V reference through a resistive REF through a resistive divider which is then fed REF show a resistor divider circuit to generate the V IXP28XX Network Processor QDR SRAM CONTROL Signal D1 3995-01 Spacing D1 D2 between Thickness ...
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... IXP28XX Network Processor QDR SRAM Figure 42. QDR SRAM V REF U61 ® ntel XP2800 Network Processor VREF_QDR0 VREF_QDR0 VREF_QDR1 VREF_QDR1 VREF_QDR2 VREF_QDR2 VREF_QDR3 VREF_QDR3 Figure 43. Resistive QDR V VDDQ 1.5 V 549 0603 Package 549 0603 Package Note: A separate resistive voltage divider should be used for each QDR SRAM channel; ...
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... In certain cases it may be desirable to implement a connector in the QDR interface to accommodate a third-party QDRII-LA1-compliant coprocessor or an upgradable QDR memory module. The Intel BKM for this is to provide the IXP28XX QDR interface through shrouded 114-pin Mictor* connector. The connector has all the QDR signals from a single channel and JTAG interface ...
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... IXP28XX Network Processor QDR SRAM Figure 45. Address, D, CONTROL, Q, and K-Clocks Topologies Intel RPE#, WPE#, BWE# Intel (On-Die Termination 50Ω) Table 33 provides routing guidelines for the TCAM/SRAM/coprocessor interface base card. Table 33. TCAM/SRAM/Coprocessor Interface Guidelines (Address, D, CONTROL, Q, and K- Clocks) Parameter Signal Group Topology ...
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... Reference Plane Characteristic Trace Impedance Nominal Trace Width Nominal Trace Separation for group Group spacing IXP28XX breakout guideline trace length Hardware Design Guide ® Intel IXP2800 Driver Cout, Clock C, C# ® IXP2800 Receiver Cin, Clock CIN, CIN# Ω TCAM/SRAM/coprocessor C, C#, CIN, and CIN# Clocks ...
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... Performance is at 250+ MHz. Figure 47. QDR SRAM Routing Recommendations ® Intel Network Processor * Note: Loopback clock length is determined from paper analysis. Actual implemented length may vary and should be determined by performing a detailed timing analysis using extracted layout parasitics. 4.8.1 Routing for a Four-QDR SRAM Topology For topologies using four loads during a read, only one SRAM drives the bus, and the stub to the other SRAM causes a reflection that effectively reduces the data-valid window ...
Page 85
... SRAM load. Figure 48. Four-QDR SRAM Load Routing Recommendations Data, Controller, ® Intel IXP2800 Network Processor * Note: Loopback clock length is determined from paper analysis. Actual implemented length may vary and should be determined by performing a detailed timing analysis using extracted layout parasitics ...
Page 86
... IXP28XX network processor to SRAM (C, K, SA, D, and R/W_BW). Figure 51 illustrates the trace length from SRAM to the IXP28XX network processor (Q data). 86 K/K#0 CIN/CIN#0 D[17:0] SA[21:0] W[1:0] ® Intel IXP2800 W#0/R#0 QDR Channe l W#/R#1 K/K#1 CIN/CIN#1 Loopback Clock D[17:0] Q[17:0] ...
Page 87
... C and C_N etch lengths are identical. In practice, they may vary by a mil or Hardware Design Guide ® Intel IXP2800 Network Processor eL1 L2 Die Internal Package Length ® Intel IXP2800 Network Processor eL6 L5 Die Internal Package Length L# is the length of etch on the printed circuit board (PCB). The label, IXP28XX Network Processor QDR SRAM L3 ...
Page 88
... Therefore, the total capacitive load at the end of the line on C[0] is two SRAMs for 10 pF (minimum) and 12 pF (maximum). The total capacitive load at the end of the line one IXP28XX network processor for 5 pF (minimum) and 10 pF (maximum). The total capacitive load at the end of the line on C[1] is one IXP28XX network processor for 5 pF (minimum) and 10 pF (maximum) ...
Page 89
... IXDP2800 Advanced Development Platform: • Figure 52, “QDR 0 Routing on Layer 13 - Adjacent QDR Clamshell Pairs” • Figure 53, “QDR 1 Routing on Layer 12 - Adjacent QDR Clamshell Pairs” Figure 52. QDR 0 Routing on Layer 13 - Adjacent QDR Clamshell Pairs Hardware Design Guide IXP28XX Network Processor QDR 0 routing on layer 13 QDR SRAM 89 ...
Page 90
... IXP28XX Network Processor QDR SRAM Figure 53. QDR 1 Routing on Layer 12 - Adjacent QDR Clamshell Pairs 4.9 IXDP2800 TCAM Implementation This section describes the placement and routing implementation for the TCAM and QDR SRAM. 4.9.1 TCAM and QDR SRAM Placement Figure 54 illustrates TCAM and QDR SRAM placement. ...
Page 91
... Figure 54. TCAM and QDR SRAM Placement TCAM footprint (same power pin ball-out as QDR SRAM) Hardware Design Guide QDR SRAM Footprints IXP28XX Network Processor QDR SRAM Center of routing "T" B3423-01 91 ...
Page 92
... Only terminate lines on IXP28XX network processor drives • OUTCLK/OUTCLK_L is 4 – 4.5 inches • 250+ MHz performance Figure 55. Routing Recommendations for QDR SRAM and TCAM Routing ® Intel IXP2800 Network Processor 92 0.75V 100 Ohms 0.25" 0.75" - 1.0" 1.5'" - 2.0" ...
Page 93
... QDR SRAM and TCAM Routing The following figures illustrate QDR SRAM and TCAM routing: • Figure 56, “QDR Signal from IXP28XX Network Processor to Tee Point on Layer 12” • Figure 57, “QDR Signal Tee Point Arms Routed on Signal Layers 4 and 13” Figure 56. ...
Page 94
... Only CIN[0] is used to derive the read capture clock. — The CIN[1] pin can be used to terminate the clock and this I/O pad is controllable via the RCOMP registers. Refer to the Intel® IXP2400 and IXP2800 Network Processor Programmer’s Reference Manual for more details. ...
Page 95
... Note: If the flight delay of the target PCB is not 180 ps/in then the ratio, (154/180), must be modified accordingly, i.e., the denominator would be changed to reflect the actual flight delay. Hardware Design Guide IXP28XX Network Processor QDR SRAM Table 35 must be adjusted to ...
Page 96
... IXP28XX Network Processor QDR SRAM Table 35. Package Trace Lengths for QDR Signals (Sheet Metric English Signal Units Units (mm) (in) QDR0_Q_H[16] 15.959 0.628 QDR0_Q_H[2] 14.754 0.581 QDR0_Q_H[3] 14.63 0.576 QDR0_C_H[1] 13.75 0.541 QDR0_C_L[1] 13.75 0.541 QDR0_CIN_H[0] 13.5 0.531 QDR0_CIN_H[1] 13.5 0.531 QDR0_CIN_L[0] 13 ...
Page 97
... QDR0_A_H[23] 7.147 0.281 QDR0_A_H[10] 6.968 0.274 QDR0_A_H[14] 6.962 0.274 QDR0_A_H[17] 6.88 0.271 QDR0_WPS_L[0] 6.861 0.270 QDR0_D_H[0] 6.521 0.257 IXP28XX Network Processor QDR SRAM Metric English Signal Units Units (mm) (in) QDR0_A_H[11] 6.387 0.251 QDR0_WPS_L[1] 6.368 0.251 QDR0_D_H[6] 6.312 0.249 QDR0_A_H[20] 6.193 ...
Page 98
... IXP28XX Network Processor QDR SRAM Table 35. Package Trace Lengths for QDR Signals (Sheet Metric English Signal Units Units (mm) (in) QDR1_K_H[1] 11.5 0.453 QDR1_K_L[1] 11.5 0.453 QDR1_D_H[7] 11.265 0.444 QDR1_A_H[4] 11.264 0.443 QDR1_A_H[13] 11.257 0.443 QDR1_D_H[9] 11.257 0.443 QDR1_WPS_L[1] 11.257 0.443 QDR1_A_H[0] 11 ...
Page 99
... QDR3_D_H[3] 6.247 0.246 QDR3_A_H[3] 6.007 0.236 QDR3_RPS_L[1] 6.007 0.236 QDR3_A_H[19] 6.003 0.236 QDR3_A_H[16] 6.002 0.236 QDR3_A_H[7] 6.001 0.236 QDR3_A_H[13] 6 0.236 QDR3_A_H[8] 6 0.236 QDR3_A_H[11] 5.996 0.236 QDR3_D_H[2] 5.981 0.235 IXP28XX Network Processor QDR SRAM Metric English Signal Units Units (mm) (in) 99 ...
Page 100
... IXP28XX Network Processor QDR SRAM 100 Hardware Design Guide ...
Page 101
... MSF (SPI-4/CSIX/FC) 5.1 Media and Switch Fabric Interface The Media and Switch Fabric (MSF) Interface connects the Intel Network Processor to a physical layer device (PHY) and/or a Switch Fabric Interface. The MSF consists of the following external interfaces: • Receive and transmit interfaces, each of which can be individually configured for either the SPI-4 Phase 2 (System Packet Interface PHY or the CSIX-L1 protocol to a switch fabric. • ...
Page 102
... CSIX-L1 (Common Switch Interface, Level 1) defines an interface between a Traffic Manager (TM) and a Switch Fabric (SF) for ATM, IP, MPLS, and Ethernet, or similar data communication applications. The Network Processor Forum (NPF) controls the CSIX-L1 specification (available at http://www.npforum.org and www.csix.org). The unit of information transferred between Traffic Managers and Switch Fabrics is called a CFrame, of which there are three categories: • ...
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... FCIFIFO Intel IXP2800 CSIX RX Network Switch Processor Fabric Interface Flow Control TX Flow FCEFIFO Control Egress RX Intel IXP2800 Network Processor CSIX TX CSIX Flow Control Interface: Full Duplex Mode IXP28XX Network Processor MSF (SPI-4/CSIX/FC) FCIFIFO CSIX RX Switch Fabric Interface Serial Flow Control Bus ...
Page 104
... IXP28XX Network Processor MSF (SPI-4/CSIX/FC) 5.2 Routing Recommendations for LVDS Signals 5.2.1 LVDS Trace Requirements The following is a list of LVDS trace requirements: • Differential signals must be routed as pairs with a 100-Ω differential impedance. • Each leg of a differential pair should be matched by length, within a tolerance of 10 mils. ...
Page 105
... GND. • Terminate unused inputs to their inactive states by using the termination guide above. Termination rules are also discussed in detail in the MSF pin description section of the IXP2800 and Intel® IXP2850 Network Processors Datasheet. 5.2.4 LVDS Routing Example Figure 60 illustrates LVDS routing as signal pairs with 15-mil trace spacing and an 11-mil air gap ...
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... Figure 61 illustrates the connections between the IXP28XX network processor and an LVDS load device showing two unique, connected PCBs: Figure 61. Topology 1 - Two Unique PCBs Connected Intel IXP2800 Network Processor Table 36 provides network length results for Topology 1. The table illustrates the resulting data EYE opening from simulations of the topology shown in Table 36 ...
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... Table 37. Topology 2 Network Length Results Transfer Net FLOW_CONTROL FLOW_CONTROL_CLK Hardware Design Guide Topology 2 Two unique PCBs and the signal loops from PCB1 to PCB2 back to PCB1 with a connector in each path ® Intel Connector IXP2800 Network Processor L3 RX Connector L1 (inches) L2 (inches) L3 (inches 0.4 ...
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... IXP28XX Network Processor MSF (SPI-4/CSIX/FC) 5.4 Package Trace Lengths for LVDS_Diff Signals Table 38 provides package trace lengths for LVDS_Diff signals, listed by decreasing lengths. For designs that implement dynamic deskew via training, matching of trace lengths through the package is not required as the deskew logic will correct this mismatch. For designs that implement static deskew, trace length-matching through the package may be required ...
Page 109
... FC_TXCPAR_L 9.44 0.372 FC_TXCPAR 9.437 0.372 SPI4_RDAT[9] 8.974 0.353 SPI4_RDAT_L[9] 8.971 0.353 FC_TXCSOF 8.904 0.351 FC_TXCSOF_L 8.903 0.351 IXP28XX Network Processor MSF (SPI-4/CSIX/FC) Metric English Signal Units Units (mm) (in) SPI4_TDAT_L[0] 6.571 0.259 SPI4_TDAT[0] 6.563 0.258 FC_TXCDAT[3] 6.463 0.254 FC_TXCDAT_L[3] 6.463 ...
Page 110
... IXP28XX Network Processor MSF (SPI-4/CSIX/FC) 110 Hardware Design Guide ...
Page 111
... Master Access (Intel XScale • Two DMA Channels • Mailbox and Doorbell Registers for Intel XScale • PCI Arbiter The network processor can be configured to act as a PCI central function (for use in a stand-alone system), where it provides the PCI reset signal add-in device, where it uses the PCI reset signal as the chip reset input ...
Page 112
... PCI Bus ® Intel 21154 PCI-PCI Bridge IDSEL = PPCI_AD<20> 32-bit 33-MHz PCI Bus Media Interface IDSEL = SPCI_AD<21> IDSEL = SPCI_AD<20> NIC IDSEL = SPCI_AD<19> Egress ® Intel IXP28XX Platform IDSEL = PPCI_AD<23> Switch Fabric Interface IDSEL = SPCI_AD<22> NIC B3928 Hardware Design Guide ...
Page 113
... Maximum = 4200 mils Maximum = 4500 mils Maximum = 50 mils Maximum = 1200 mils Maximum = 2500 mils 8 Vias IXP28XX Network Processor Egress Intel IDSEL ® Egress Intel IXP28XX ® Platform Intel 21154 ® PCI-to-PCI ridge F Intel 21555 ® PCI-to-PCI ridge 3926-02 Routing Guidelines PCI 113 ...
Page 114
... Trace Length A Trace Length B Resistor R S Maximum Count per Signal 6.2.1.3 Address/Data Signals with IDSEL Figure 66 illustrates the topology for address/data signals with IDSEL (showing only the ingress IXP28XX network processor). 114 Parameter Clock Point-to-Point Dual-referenced, PWR–SIG–GND 60 Ω ± 10% 3 ...
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... Maximum = 50 mils Maximum = 1200 mils Maximum = 2500 mils Maximum = 100 mils Maximum = 2000 mils 84 Ω ± 10% 10 vias IXP28XX Network Processor Egress Intel ® IXP28XX Platform D Intel 21154 ® PCI-to-PCI ridge F Intel 21555 ® PCI-to-PCI ridge 3927-02 Routing Guidelines PCI 115 ...
Page 116
... Spacing to Other Groups 116 B A SWF Connector Parameter SPCI Address/Data Daisy Chain Dual-referenced, PWR–SIG–GND 60 Ω ±10% 3.5 mils 9 mils 20 mils Media Connector PMC Connector H Ingress ® Intel 82559 NIC I Egress ® Intel 82559 NIC B3962-01 Routing Guidelines Hardware Design Guide ...
Page 117
... Maximum Via Count per Signal 6.2.2.2 SPCI Clock Signals Figure 68 illustrates the topology for SPCI clock signals. Figure 68. SPCI Clock Signals Topology ® Intel 21154 PCI-to-PCI Bridge Table 43 provides routing guidelines for the SPCI clock signals group parameters. Table 43. SPCI Clock Signals Group Guidelines ...
Page 118
... SPCI Address/Data Signals with IDSEL Signal Topology A Intel 21154 ® PCI-to-PCI ridge 1. Only the 211154 PCI-PCI bridge case is shown. 118 Intel IDSEL C SWF Connector D E Media Connector 21154 ® PMC Connector I Ingress Intel 82559 ® NIC J Egress Intel 82559 ® NIC 3963-01 Hardware Design Guide ...
Page 119
... Maximum = 200 mils Maximum = 5200 mils Maximum = 500 mils Maximum = 7000 mils Maximum = 200 mils Maximum = 4500 mils Maximum = 200 mils Maximum = 1200 mils Maximum = 150 mils Maximum = 2000 mils 84 Ω ± 10% 12 vias IXP28XX Network Processor PCI Routing Guidelines 119 ...
Page 120
... IO 6.2.3.1 cPCI Signals Figure 70 illustrates the topology for the cPCI signal. Figure 70. cPCI Signal Topology ® Intel 21555 PCI-to-PCI Bridge Table 45 provides routing guidelines for the cPCI signal group parameters. Table 45. cPCI Signal Group Guidelines Signal Group Topology ...
Page 121
... Network Network Processor Processor Ingress Egress NPU Domain ® Intel 64 bits only Non- Secondary PCI Primary PCI side of the side of the Intel 21555 Intel 21154 NTB NTB IXP28XX Network Processor 82559 NC ® Intel 82559 NC 21154 Transparent PMC Bridge Fabric Utility Domain ...
Page 122
... IXP28XX Network Processor PCI Figure 72. 64-Bit PCI Bus Routing Between Processors 64-bit PCI bus routing between processors 122 Hardware Design Guide ...
Page 123
... Figure 73 illustrates 64-bit PCI bus routing from the IXP28XX network processor to the bridge. Figure 73. 64-bit PCI Bus Routing from IXP28XX Network Processor to Bridge Hardware Design Guide 64-bit PCI bus routing from IXP28XX Network Processor to bridge IXP28XX Network Processor PCI 123 ...
Page 124
... IXP28XX Network Processor PCI 6.5 Package Trace Lengths for PCI Signals Table 46 provides package trace lengths for PCI signals. Note typically not required to account for the package trace length for PCI interface signals. The flight time on the package substrate is 154ps/in which differs from the flight delay of standard FR4, typical 180ps/in ...
Page 125
... PCI_AD[62] 3.817 0.150 PCI_AD[63] 13.417 0.528 PCI_AD[7] 5.076 0.200 PCI_AD[8] 10.682 0.421 PCI_AD[9] 12.02 0.473 PCI_CBE_L[0] 11.033 0.434 IXP28XX Network Processor PCI Metric English Signal Units Units (mm) (in) PCI_RST_L 5.807 0.229 PCI_SERR_L 4.71 0.185 PCI_STOP_L 16.576 0.653 PCI_TRDY_L 9.061 ...
Page 126
... IXP28XX Network Processor PCI 126 Hardware Design Guide ...
Page 127
... Therefore, an external set of buffers is needed to latch the address; two chip selects are provided – see Note: To meet interface timing requirements, Intel suggests the external interface logic be implemented in a high speed CPLD (Complex Programmable Logic Device), as shown in Figure 74 ...
Page 128
... Slowport includes a programmable timing control mechanism for this purpose. For Slowport programming and timing setup, refer to the Intel® IXP2400 and IXP2800 Network Processor Programmer’s Reference Manual. The Slowport unit contains two types of interface and two ports: • ...
Page 129
... Debug Display Media Interface Control Switch Fabric Interface Control Address A<9:2> Latches NetROM Connector Address A<17:10> Latches Address A<24:18> Latches A<1:0> D<7:0> IXP28XX Network Processor Slowport 28F128J3A Flash 8-bit Interface 16 M yte NetROM 3964-01 ® Intel 8F128J3A 16 MByte 8-bit Flash B0183-01 129 ...
Page 130
... IXP28XX Network Processor Slowport 7.1.1 Slowport Signals The Slowport signals are defined in Table 47. Signal Description Signal Name SP_AD[7:0] SP_OE_L SP_CP/SP_A0 SP_DIR/SP_A1 SP_ALE_L SP_CS[1:0] SP_RD_L SP_WR_L SP_ACK SP_CLK 7.1.1.1 Topology and Routing The following sections describe the topology and routing guidelines for Slowport interface control signals, clocks, and address/data signals ...
Page 131
... Figure 78. Slowport Control Signals Topology Egress Intel IXP2800 ® Interface Table 48 provides routing guidelines for the Slowport control signals. Table 48. Slowport Control Signals Routing Guidelines Parameter Signal Group Topology Reference Plane Characteristic Trace Impedance Nominal Trace Width Nominal Trace Separation Group spacing ...
Page 132
... IXP28XX Network Processor Slowport 7.1.1.1.2 Slowport Clock Signals Figure 79 illustrates the topology for the Slowport clock. Figure 79. Slowport Clock Topology Intel ® XP2800 Interface Table 49 provides routing guidelines for the Slowport media interface clock signals. Table 49. Slowport Clock Signals Guideline Parameter ...
Page 133
... SP_CS[0], while access to the upper 32-Mbyte region of microprocessor space is decoded with SP_CS[1]. Using these two signals, the glue logic distinguishes between accesses to each interface. Refer to the Intel® IXP2800 Network Processor Hardware Reference Manual for additional details about the Slowport unit. ...
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... The least significant byte (LSB) of the address is delivered first and the most significant byte (MSB) is presented last. Note: Timing diagrams for all supported modes are provided in the Slowport unit section of the Intel® IXP2800 Network Processor Hardware Reference Manual. We recommend that you consult the HRM and review all of the timing diagrams in that section ...
Page 135
... Figure 81. Slowport Application Topology SP_RD_L SP_WR_L SP_CS_L[0] SP_CS_L[1] SP_A[1:0] SP_AD[7:0] SP_ALE_L SP_CLK ® Intel IXP2800 Network Processor SP_ACK_L Figure 82. Mode 0 Single Write Transfer for a Fixed-timed Device SP_CLK SP_ALE_L SP_CS_L [1:0] SP_WR_L SP_RD_L SP_A[1:0] SP_AD[7:0] Hardware Design Guide CE# D[7:0] 74f377 Clock CP Q[7:0] ...
Page 136
... Microprocessor Interface Logic The Slowport microprocessor interface can be configured to support 8-, 16-, and 32-bit devices. Refer to the Intel® IXP2400 and IXP2800 Network Processor Programmer’s Reference Manual for detailed information about each mode. As with the flash interface, external logic must be implemented to latch the address. Since this ...
Page 137
... Additionally, there are four Hardware Design Guide <= 2'b00; <= ale_cnt + 1; <= 2'b00; <= 25'h0000000; //synopsys full_case parallel_case latched_add[7:0] <= sp_ad_in; latched_add[15:8] <= sp_ad_in; latched_add[23:16] <= sp_ad_in; latched_add[24] <= sp_ad_in[0];//for 25-bit address space Example 3 <= 32'h00000000; <= sp_ad_in; <= latched_add[7:0]; <= latched_add[15:8]; <= latched_add[23:16]; IXP28XX Network Processor Slowport shows a coded example of this logic. 137 ...
Page 138
... Note: The actual protocol of these control signals varies depending on the interface configuration mode ( 4). The remainder of this section concentrates on the Mode 3 protocol, the mode that would be used to interface to the Intel Figure 84 shows an example of discrete components and their associated signal connections that could be used to implement the glue logic ...
Page 139
... Figure 84. An Interface Topology with Intel / AMCC* SONET/SDH Device SP_RD_L SP_WR_L SP_CS_L[1] SP_ACK_L SP_AD[7:0] SP_ALE_L SP_CLK ® Intel IXP2800 Network Processor SP_CP SP_OE_L SP_DIR * Other names and brands may be claimed as property of others. Hardware Design Guide CE# D[7:0] 74F377 CP Q[7:0] Clock ADDR[10:8] Driver ...
Page 140
... Note: The IXP28XX CSR Transmit Enable Register (SP_TXE) can be used to delay the data and relevant Slowport signals in relation to the SP_CLK. For programming information, refer to the Intel® IXP2800 Network Processor Hardware Reference Manual. 140 ...
Page 141
... Hardware Design Guide Rise of SP_CP TXE+1 delay Example example implementation of the logic. <= 32'h0000_0000; <= sp_ad_in; <= data[31:24]; <= data[23:16]; <= data[15:8]; <= uP_rd_data; IXP28XX Network Processor Slowport Internal bus clock Rise of SP_CLK 3 7d TXE in this run is 1 and delays the change in data by TXE+1 internal bus clocks B3924-02 141 ...
Page 142
... Slowport interface signals presented to the glue logic during a read transaction. Note: The IXP28XX CSR Receive Enable Register (SP_RXE) can be used to advance the data sampled internally before the rising edge of the SP_CLK. For programming SP_RXE, refer to the Intel® IXP2400 and IXP2800 Network Processor Programmer’s Reference Manual. ...
Page 143
... After the data is captured, the logic must also unpack the data back to the IXP28XX network processor at eight bits per transfer (MSB to LSB) onto the SP_AD. This is accomplished by the glue logic driving the first byte of the read data back to the network processor on the SP_RD_OUT bus when the signal SHIFT_EN is asserted. ...
Page 144
... On the clock cycle after the read signal is de-asserted from the downstream device, the glue logic will drive the first byte of data onto the SP_AD bus since the IXP28XX network processor does not pulse the SP_CP signal to promote the first read. The remaining three bytes of data are shifted out on the rising edge of the SP_CP signal to complete the 32-bit transfer ...
Page 145
... The data packing/unpacking logic examples were chosen to provide an interface to an Intel/AMCC* device. While the other modes have subtle protocol and interface signal differences, the logic used for address latching and data packing/unpacking should be essentially the same. ...
Page 146
... IXP28XX Network Processor Slowport 146 Hardware Design Guide ...
Page 147
... Product Name RPIXP2800BA RPIXP2800BB RPIXP2800BC RPIXP2800BA RPIXP2800BB RPIXP2800BC RPIXP2800BA RPIXP2800BB RPIXP2850BA RPIXP2850BB RPIXP2850BC RPIXP2850BA RPIXP2850BB RPIXP2850BC RPIXP2850BA RPIXP2850BB 1. Not applicable — production-qualified devices are not marked with a QDF number. Hardware Design Guide Figure Stepping QDF Number Part Number B0 Q668 B0 Q669 B1 Q853 B1 Q808 ...
Page 148
... IXP28XX Network Processor Mechanical/Packaging Figure 89. Intel® IXP2800 Network Processor Package Marking Figure 90. Intel® IXP2850 Network Processor Package Marking 148 RPIXP2800xx <FPO#> INTEL XXXX M C PHILIPPINES RPIXP2850xx <FPO#> INTEL M C XXXX PHILIPPINES Level 1 Name Intel Legal Country of Origin 2D Matrix (encoded assembly lot ...
Page 149
... Package Dimensions The network processor package dimensions are shown in detailed in Table 51. Figure 91. Intel® IXP2800 or Intel® IXP2850 Network Processor Package Ball Grid Array Pin 1 corner Figure 92. Intel® IXP2800 or Intel® IXP2850 Network Processor Package Side View Seating Plane ...
Page 150
... IXP28XX Network Processor Mechanical/Packaging Figure 93. Intel® IXP2800 or Intel® IXP2850 Network Processor Package Top View Table 51. Intel® IXP2800 or IXP2850 Network Processor Package Dimensions Symbol Note: All dimensions are in millimeters (mm). 150 E F1 Top View Minimum Maximum 3.891 4.565 0.40 0.60 2 ...
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Index A Address and data signals PCI PPCI 112 PCI SPCI 116 with IDSEL 118 Slowport 132 routing guidelines 133 topology 133 Address topology QDR SRAM 65 C Clock PCI PCCI signals 113 PCI SPCI signals 117 QDR SRAM topologies ...
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Index trace lengths LVDS_Diff signals 108 PCI signals 124 Packaging specifications 147 PCI address/data signals with IDSEL 114 controller 111 CPCI. See CPCI. design review checklist 121 interface 111 package trace lengths 124 PPCI. See PPCI. routing examples 121 SPCI ...
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PROM interface address ...
Page 154
Index 154 ...