RPIXP2850BB Intel, RPIXP2850BB Datasheet - Page 15

• Manufacturer Part Number: RPIXP2850BB
• Manufacturer: Intel

Specifications of RPIXP2850BB

• Operating Supply Voltage (typ): 1.3/1.5/2.5/3.3V
• Operating Supply Voltage (max): 1.575/2.7/3.465V
• Operating Supply Voltage (min): 1.235/2.3/3.135V
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

Table 3.
Hardware Design Guide
Acronyms and Terminology (Sheet 2 of 3)
DRCG
ECC
EEPROM
LVDS
MAC
MSF
NA
NIC
NPF
OIF
PCB
PCI
PHY
PGA
PLL
POS
PPCI
PVT
QDR SRAM
RDRAM
RIMM*
RPE
RSL
SDH
SF
SHA-1
SPCI
SPI-4
Striping
Acronym/Terminology
Direct Rambus* Clock Generator
Error Correction Code
Electrically Erasable Programmable Read-only Memory
Low-Voltage Differential Signaling
Medium Access Control, a 48-bit number unique to each LAN network interface
card (NIC)
Media Switch Fabric
Not applicable
Network Interface Card
Network Processor Forum; organized to facilitate the development of next-
generation networking and telecommunications products based on network
processing technologies
Optical Internetworking Forum
Printed circuit board
Peripheral Component Interconnect
physical layer device
pin grid array
Phase Lock Loop
Packet over SONET
Primary PCI, a 64-bit PCI bus operating at 33 or 66 MHz. This bus connects the
ingress and egress IXP28XX network processor to the master and slave PCI-PCI
bridge chips.
Process/Voltage/Temperature
Quad Data Rate Static Random Access Memory
Rambus* Dynamic Random Access Memory
Rambus* In-line Memory Module used with RDRAM chips developed by
Rambus, Inc.
Read Port Enable, a type of control signal that is active low
Rambus* Signaling Level
Synchronous Digital Hierarchy, a set of international fiber optic transmission
standards
Switch Fabric
Secure Hash Algorithm 1
Secondary PCI, a 32-bit bus operating at 33 MHz
Interface for packet and cell transfer between a physical layer (PHY) device and
a link layer device (the IXP28XX network processor), for aggregate bandwidths of
OC-192 ATM and Packet over SONET/SDH (POS), as well as 10 Gb/s Ethernet
applications.
Hardware interleaving of addresses to provide balanced access to all populated
channels; the interleave size is 128 bytes. Interleaving helps to maintain
utilization of available bandwidth by spreading consecutive accesses to multiple
channels. The interleaving is done in the hardware so that the three channels
appear to software as a single contiguous memory space.
Definition
IXP28XX Network Processor
Introduction
15