RPIXP2850BB Intel, RPIXP2850BB Datasheet - Page 152

• Manufacturer Part Number: RPIXP2850BB
• Manufacturer: Intel

Specifications of RPIXP2850BB

• Operating Supply Voltage (typ): 1.3/1.5/2.5/3.3V
• Operating Supply Voltage (max): 1.575/2.7/3.465V
• Operating Supply Voltage (min): 1.235/2.3/3.135V
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

Index
Packaging specifications 147
PCI
Power
Power-on di/dt profiles 30
Power-up
PPCI
Processor
Q
QDR
152
trace lengths
address/data signals with IDSEL 114
controller 111
CPCI. See CPCI.
design review checklist 121
interface 111
package trace lengths 124
PPCI. See PPCI.
routing examples 121
SPCI 116
ratings
requirements 17
supply
considerations when using NexMod* memory modules
power supply regulation 25
sequence 36
address/data signals 112
bus interface 112
clock signals 113
controller escape routing 41
input timing 64
output timing 64
power-on di/dt profiles 30
short channel routing 49
three-channel controller to HCD NexMod* RDRAM
clocking 54
interface examples 60
signal group package trace length 64
SRAM
LVDS_Diff signals 108
PCI signals 124
maximum 17
minimum 17
requirements 17
decoupling 25
power-up regulation 25
regulation 25
subsystem 27
supply voltage 24
address topology 65
clock topologies
connections 57
control topologies
37
routing 46
C, C#, CIN, CIN# 74
K, K# 71
RPE#, WPE#, BWE# 76
QDRII SRAM, Loopclock length 85
R
Rambus*
Ratings, power 17
RDRAM
Requirements, power 17
Routing
RSL, trace requirements and recommendations 35
S
Short channel routing, processor 49
Simulation results for LVDS signals 106
Slowport
trace requirements 65
channel design 35
controller footprint and via placement 38
crosstalk 36
third-party sources 36
unused channel guidelines 36
processor three-channel controller to HCD NexMod*
subsystem
four-QDR SRAM topology 84
LVDS
PCI examples 121
processor
QDR
RSL 35, 36
short channel 49
Slowport 130
address latch logic 136
DataIn topology 70
DataOut topology 68
design review checklist 94
interface 57
output timing specifications 64
placement with TCAM 90
routing 84
using x9 versus x18 parts 58
VREF generation 79
design 33
implementation options 34
example 105
signals recommendations 104
controller escape 41
three-channel controller to HCD NexMod*
SRAM 84
address and data signal guidelines 133
alternating layers 89
recommendations 84
rules 65
with TCAM 93
RDRAM 46
alternating layers 89
rules 65
recommendations 92
RDRAM 46