EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 160
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C2N
Manufacturer Part Number
EP3SL150F1152C2N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C2N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2409
EP3SL150F1152C2NES
EP3SL150F1152C2NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3SL150F1152C2N
Manufacturer:
ALTERA
Quantity:
20 000
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6–12
Table 6–7. Stratix III Device PLLs and PLL Clock Pin Drivers (Part 2 of 2)
Clock Output Connections
Stratix III Device Handbook, Volume 1
CLK13
CLK14
CLK15
PLL_L1_CLKp
PLL_L1_CLKn
PLL_L4_CLKp
PLL_L4_CLKn
PLL_R1_CLKp
PLL_R1_CLKn
PLL_R4_CLKp
PLL_R4_CLKn
Notes to
(1) For compensated PLLs input, only the dedicated CLK pins in the same I/O bank as the PLL used are compensated inputs.
(2) If both PLL_<L1/L4/R1/R4>_CLKp and PLL_<L1/L4/R1/R4>_CLKn pins are not used as a pair of differential clock pins, they can
(3) For single-ended clock input, CLKn pins use the global network to drive the PLLs.
Dedicated Clock Input Pin
be used independently as single-ended clock input pins.
Table
(CLKp/n pins)
6–7:
(2)
(2),(3)
(2)
(2),(3)
(2)
(2),(3)
(2)
(2),(3)
PLLs in Stratix III devices can drive up to 20 regional clock networks and four global
clock networks. Refer to
The Quartus II software automatically assigns PLL clock outputs to regional or global
clock networks.
Table 6–8
Table 6–8. PLL Connectivity to GCLKs on Stratix III Devices (Part 1 of 2)
GCLK0
GCLK1
GCLK2
GCLK3
GCLK4
GCLK5
GCLK6
GCLK7
GCLK8
GCLK9
GCLK10
GCLK11
Clock Network
v
v
lists how the PLL clock outputs connect to GCLK networks.
L1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
L2
v
v
v
v
—
—
—
—
—
—
—
—
L1
L3
—
—
—
—
—
—
—
—
—
—
—
Table 6–8
v
v
v
v
L2
—
—
—
—
—
—
—
—
—
—
—
—
—
v
v
—
—
—
—
L4
v
v
v
v
L3
—
—
—
—
—
—
—
—
B1
—
—
—
—
—
—
—
—
—
—
—
for Stratix III PLL connectivity to GCLK networks.
v
v
v
v
L4
—
—
—
—
—
—
—
—
B2
—
—
—
—
—
—
—
—
—
—
—
PLL Number
Chapter 6: Clock Networks and PLLs in Stratix III Devices
B1
—
—
—
—
v
v
v
v
—
—
—
—
(Note 1)
R1
—
—
—
—
—
—
—
v
v
—
—
PLL Number
v
v
v
v
B2
—
—
—
—
—
—
—
—
R2
—
—
—
—
—
—
—
—
—
—
—
R1
v
v
v
v
—
—
—
—
—
—
—
—
Clock Networks in Stratix III Devices
R2
—
—
—
—
—
—
—
—
v
v
v
v
R3
—
—
—
—
—
—
—
—
—
—
—
© July 2010 Altera Corporation
(Note 1)
R3
v
v
v
v
—
—
—
—
—
—
—
—
R4
v
v
—
—
—
—
—
—
—
—
—
R4
—
—
—
—
—
—
—
—
v
v
v
v
v
v
v
T1
—
—
—
—
—
—
—
—
T1
—
—
—
—
—
—
—
—
—
—
—
—
T2
v
v
v
—
—
—
—
—
—
—
—
T2
—
—
—
—
—
—
—
—
—
—
—
—
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