EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 345

• Manufacturer Part Number: EP3SL150F1152C2N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C2N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2409; EP3SL150F1152C2NES

Chapter 11: Configuring Stratix III Devices
Fast Passive Parallel Configuration
Figure 11–5. Multiple-Device FPP Configuration Using an External Host When Both Devices Receive the Same Data
Notes to
(1) Connect the resistor to a supply that provides an acceptable input signal for all Stratix III devices on the chain. V
(2) The nCEO pins of both devices are left unconnected when configuring the same configuration data into multiple devices.
© March 2011 Altera Corporation
meet the V
(MAX II Device or
Figure
Microprocessor)
External Host
ADDR DATA[7..0]
IH
Memory
f
11–5:
specification of the I/O on the external host. It is recommended to power up all configuration system’s I/O with V
1
If you have enabled the Auto-restart configuration after error option, the nSTATUS pin
transitions from high to low and back again to high when a configuration error is
detected. This appears as a low pulse at the nSTATUS pin with a minimum pulse width
of 10 μs to a maximum pulse width of 500 μs, as defined in the t
In a multi-device FPP configuration chain, all Stratix III devices in the chain must
either enable or disable the decompression feature, design security feature, or both.
You cannot selectively enable the decompression feature, design security feature, or
both for each device in the chain because of the DATA and DCLK relationship. If the
chain contains devices that do not support design security, you should use a serial
configuration scheme.
If a system has multiple devices that contain the same configuration data, tie all
device nCE inputs to GND, and leave nCEO pins floating. All other configuration pins
(nCONFIG, nSTATUS, DCLK, DATA[7..0], and CONF_DONE) are connected to every
device in the chain. Configuration signals may require buffering to ensure signal
integrity and prevent clock skew problems. Ensure that the DCLK and DATA lines are
buffered for every fourth device. Devices must be the same density and package. All
devices start and complete configuration at the same time.
multi-device FPP configuration when both Stratix III devices are receiving the same
configuration data.
You can use a single configuration chain to configure Stratix III devices with other
Altera devices that support FPP configuration, such as other types of Stratix devices.
To ensure that all devices in the chain complete configuration at the same time, or that
an error flagged by one device initiates reconfiguration in all devices, tie all of the
device CONF_DONE and nSTATUS pins together.
For more information about configuring multiple Altera devices in the same
configuration chain, refer to
Handbook.
V
10 kΩ
CCPGM
(1)
V
CCPGM
10 kΩ
(1)
GND
CONF_DONE
nSTATUS
nCE
DATA[7..0]
nCONFIG
DCLK
Stratix III Device
Configuring Mixed Altera FPGA Chains
MSEL[2..0]
nCEO
GND
N.C. (2)
GND
Stratix III Device Handbook, Volume 1
Figure 11–5
nCE
CONF_DONE
nSTATUS
DATA[7..0]
nCONFIG
DCLK
Stratix III Device
CCPGM
STATUS
in the Configuration
should be high enough to
MSEL[2..0]
specification.
nCEO
shows a
CCPGM
GND
N.C. (2)
.
11–13