EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 433

• Manufacturer Part Number: EP3SL150F1152C2N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C2N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2409; EP3SL150F1152C2NES

Chapter 15: SEU Mitigation in Stratix III Devices
User Mode Error Detection
© March 2010 Altera Corporation
A single 16-bit CRC calculation is done on a per-frame basis. Once it has finished the
CRC calculation for a frame, the resulting 16-bit signature is hex 0000 if there are no
detected CRAM bit errors in a frame by the error detection circuitry and the output
signal CRC_ERROR is 0. If a CRAM bit error is detected by the circuitry within a frame
in the device, the resulting signature is non-zero. This causes the CRC engine to start
searching the error bit location.
Error detection in Stratix III devices calculates CRC check bits for each frame and
pulls the CRC_ERROR pin high when it detects bit errors in the chip. Within a frame, it
can detect all single-bit, double-bit, and three-bit errors. The probability of more than
three CRAM bits being flipped by an SEU event is very low. In general, for all error
patterns the probability of detection is 99.998%.
The CRC engine reports the bit location and determines the type of error for all
single-bit errors and over 99.641% of double-adjacent errors. The probability of other
error patterns is very low and the report of the bit flips error location is not
guaranteed by the CRC engine.
You can also read-out the error bit location through the Joint Test Action Group
(JTAG) and the core interface. You must shift these bits out through either the JTAG
instruction, SHIFT_EDERROR_REG, or the core interface before the CRC detects the
next error in another frame. If the next frame also has an error, you have to shift these
bits out within the amount of time of one frame CRC verification. You can choose to
extend this time interval by slowing down the error detection clock frequency, but this
slows down the error recovery time for the SEU event. Refer to
page 15–10
shifted out before the next error location is found, the previous error location and
error message is overwritten by the new information. The CRC circuit continues to
run, and if an error is detected, you must decide whether to complete a
reconfiguration or to ignore the CRC error.
The error detection logic continues to calculate the CRC_ERROR and 16-bit signatures
for the next frame of data regardless if any error has occurred in the current frame or
not. You must monitor these signals and take the appropriate actions if a soft error
occurs.
Error detection circuitry in Stratix III devices uses a 16-bit CRC-ANSI standard (16-bit
polynomial) as the CRC generator.
The computed 16-bit CRC signature for each frame is stored in registers within the
core. The total storage register size is 16 (number of bits per frame) × the number of
frames.
The Stratix III device error detection feature does not check memory blocks and I/O
buffers. These memory blocks support parity bits that are used to check the contents
of memory blocks for any error. The I/O buffers are not verified during error
detection because these bits use flip-flops as storage elements that are more resistant
to soft errors compared to CRAM cells.
The M144K TriMatrix memory block has a built-in error correction code block that
checks and corrects errors in the block. However, for logic array blocks (LABs) that are
used as MLAB memory blocks, they are ignored during error detection verification.
Thus, the CRC_ERROR signal may stay solid high or low depending on the error status
of the previous checked CRAM frame.
for the minimum update interval for Stratix III devices. If these bits are not
Stratix III Device Handbook, Volume 1
Table 15–6 on
15–3