EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 73
EP3SL150F1152C2N
Manufacturer Part Number
EP3SL150F1152C2N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C2N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2409
EP3SL150F1152C2NES
EP3SL150F1152C2NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3SL150F1152C2N
Manufacturer:
ALTERA
Quantity:
20 000
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Chapter 3: MultiTrack Interconnect in Stratix III Devices
Memory Block Interface
Figure 3–4. MLAB RAM Block LAB Row Interface
© October 2008 Altera Corporation
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
C4 Interconnects
The M9K RAM block local interconnect is driven by the R4, C4, and direct link
interconnects from adjacent LABs. The M9K RAM blocks can communicate with
LABs on either the left or right side through these row resources or with LAB columns
on either the right or left with the column resources. Up to 20 direct link input
connections to the M9K RAM Block are possible from the left adjacent LABs and
another 20 possible from the right adjacent LAB. M9K RAM block outputs can also
connect to left and right LABs through direct link interconnect.
M9K RAM block to logic array interface.
20
MLAB Local
Interconnect Region
20
clocks
datain
LAB Row Clocks
signals
control
MLAB
address
dataout
Stratix III Device Handbook, Volume 1
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
Figure 3–5
R4 Interconnects
shows the
3–7
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