EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 442
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C2N
Manufacturer Part Number
EP3SL150F1152C2N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C2N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2409
EP3SL150F1152C2NES
EP3SL150F1152C2NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3SL150F1152C2N
Manufacturer:
ALTERA
Quantity:
20 000
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15–12
Recovering From CRC Errors
Chapter Revision History
Table 15–8. Chapter Revision History
Stratix III Device Handbook, Volume 1
March 2010
May 2009
February 2009
October 2008
May 2008
October 2007
May 2007
November 2006
Date
The system that contains the Stratix III device must control the device reconfiguration.
After detecting an error on the CRC_ERROR pin, strobing the nCONFIG signal low
directs the system to perform the reconfiguration at a time when it is safe for the
system to reconfigure the device.
When the data bit is rewritten with the correct value by reconfiguring the device, the
device functions correctly.
While soft errors are uncommon in Altera devices, certain high-reliability applications
may require a design to account for these errors.
Table 15–8
Version
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
lists the revision history for this chapter.
Updated for the Quartus II software version 9.1 SP2 release:
■
■
Updated “User Mode Error Detection” and “CRC_ERROR Pin” sections.
■
■
■
■
■
■
■
■
■
■
■
■
Initial Release.
Updated
Minor text edits.
Updated “Error Detection Timing” section.
Removed “Referenced Documents”, Critical Error Detection”, and “CRITICAL
ERROR Pin” sections.
Updated “Introduction” and “Referenced Documents” sections.
Updated New Document Format.
Updated “Configuration Error Detection”, “User Mode Error Detection”, and “Error
Detection Timing” sections.
Updated Table 15–3, Table 15–6, and Table 15–7.
Updated Figure 15–2 and Figure 15–3.
Minor edits to Table 15–3.
Added new section “Referenced Documents”.
Added live links for references.
Minor edits to page 2, 3, 4, and 14.
Updated Table 15–5.
Table
15–6.
Changes Made
Chapter 15: SEU Mitigation in Stratix III Devices
© March 2010 Altera Corporation
Recovering From CRC Errors
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