EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 434

• Manufacturer Part Number: EP3SL150F1152C2N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C2N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2409; EP3SL150F1152C2NES

15–4
Stratix III Device Handbook, Volume 1
f
1
1
1
For more information about error detection in the Stratix III TriMatrix memory blocks,
refer to the
In order to provide testing capability of the error detection block, a JTAG instruction
EDERROR_INJECT is provided. This instruction can change the content of the 21-bit
JTAG fault injection register, used for error injection in Stratix III devices, hence
enabling testing of the error detection block.
You can only execute the EDERROR_INJECT JTAG instruction when the device is in
user mode.
Table 15–1
Table 15–1. EDERROR_INJECT JTAG Instruction
You can only execute the EDERROR_INJECT JTAG instruction at error detection
frequency 50 MHz. Refer to
about how to set the error detection frequency in the Quartus II software. For the
testing of the CRC detection block with the frequency lower than 50 MHz, contact
Altera Technical Support at www.altera.com/support.
You can create Jam™ files (.jam) to automate the testing and verification process. This
allows you to verify the CRC functionality in-system, on-the-fly, without having to
reconfigure the device. You can then switch to the CRC circuit to check for real errors
induced by an SEU.
You can introduce a single error, double errors, or double errors adjacent to each other
to the configuration memory. This provides an extra way to facilitate design
verification and system fault tolerance characterization. Use the JTAG fault injection
register with EDERROR_INJECT instruction to flip the readback bits. The Stratix III
device is then forced into error test mode.
The content of the JTAG fault injection register is not loaded into the fault injection
register during the processing of the last and the first frame. It is only loaded at the
end of this period.
You can only introduce error injection in the first data frame, but you can monitor the
error information at any time.
For more information about the JTAG fault injection register and fault injection
register, refer
EDERROR_INJECT
JTAG Instruction
lists the EDERROR_INJECT JTAG instruction.
TriMatrix Embedded Memory Blocks in Stratix III Devices
to“Error Detection Registers” on page
Instruction Code
“Error Detection Timing” on page 15–9
00 0001 0101
This instruction controls the 21-bit JTAG fault
injection register, which is used for error
injection.
Chapter 15: SEU Mitigation in Stratix III Devices
15–7.
Description
© March 2010 Altera Corporation
chapter.
User Mode Error Detection
for instructions