EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 353

• Manufacturer Part Number: EP3SL150F1152C2N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C2N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2409; EP3SL150F1152C2NES

Chapter 11: Configuring Stratix III Devices
Fast Active Serial Configuration (Serial Configuration Devices)
Figure 11–9. Multi-Device Fast AS Configuration
Notes to
(1) Connect the pull-up resistors to V
(2) Connect the repeater buffers between the Stratix III master and slave device(s) for
© March 2011 Altera Corporation
integrity and clock skew problems.
Serial Configuration
Figure
Device
11–9:
1
1
DATA
DCLK
ASDI
nCS
V
As shown in
connected with external pull-up resistors. These pins are open-drain bi-directional
pins on the devices. When the first device asserts nCEO (after receiving all of its
configuration data), it releases its CONF_DONE pin. The subsequent devices in the
chain keep this shared CONF_DONE line low until they have received their
configuration data. When all target devices in the chain have received their
configuration data and released CONF_DONE, the pull-up resistor drives a high level
on this line and all devices simultaneously enter initialization mode.
If an error occurs at any point during configuration, the nSTATUS line is driven low
by the failing device. If you enable the Auto-restart configuration after error option,
reconfiguration of the entire chain begins after a reset time-out period (maximum of
100 µs). If the Auto-restart configuration after error option is turned off, the external
system must monitor nSTATUS for errors and then pulse nCONFIG low to restart
configuration. The external system can pulse nCONFIG if it is under system control
rather than tied to V
If you have enabled the Auto-restart configuration after error option, the nSTATUS pin
transitions from high to low and back again to high when a configuration error is
detected. This appears as a low pulse at the nSTATUS pin with a minimum pulse width
of 10 μs to a maximum pulse width of 500 μs, as defined in the t
While you can cascade Stratix III devices, you cannot cascade or chain together serial
configuration devices.
CCPGM
10 kΩ
(1)
CCPGM
Buffers (2)
V
CCPGM
at 3.3-V supply.
10 kΩ
Figure
(1)
GND
V
CCPGM
10 kΩ
11–9, the nSTATUS and CONF_DONE pins on all target devices are
CCPGM
(1)
Stratix III FPGA Master
nSTATUS
CONF_DONE
nCONFIG
nCE
DATA0
DCLK
nCSO
ASDO
.
MSEL2
MSEL1
MSEL0
nCEO
V
CCPGM
DATA[0]
GND
and
DCLK
nSTATUS
CONF_DONE
nCONFIG
nCE
DATA0
DCLK
Stratix III FPGA Slave
Stratix III Device Handbook, Volume 1
.
This prevents any potential signal
STATUS
MSEL2
MSEL1
MSEL0
nCEO
specification.
GND
V
N.C.
CCPGM
11–21