EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 330
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C2N
Manufacturer Part Number
EP3SL150F1152C2N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C2N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2409
EP3SL150F1152C2NES
EP3SL150F1152C2NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3SL150F1152C2N
Manufacturer:
ALTERA
Quantity:
20 000
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10–6
Stratix III Device Handbook, Volume 1
f
1
The POR circuit does not monitor the power supplies listed in
Table 10–3. Power Supplies That Are Not Monitored by the POR Circuitry
During power up, all power supplies listed in
to monotonically reach their full-rail values within t
The POR specification is designed to ensure that all the circuits in the Stratix III device
are at certain known states during power up.
The POR signal pulse width is programmable using the PORSEL input pin. When
PORSEL is set to low, the POR signal pulse width is set to 100 ms. A POR pulse width
of 100 ms allows serial flash devices with 65 ms to 100 ms internal POR delay to be
powered up and ready to receive the nSTATUS signal from Stratix III. When the
PORSEL is set to high, the POR signal pulse width is set to 12 ms. A POR pulse width
of 12 ms allows time for power supplies to ramp-up to full rail.
For more information about the POR specification, refer to the
Characteristics
V
V
V
V
V
Note to
(1) The nominal voltage for V
C CIO
C CA _PLL
C CD_P LL
C C_C LK IN
C CB AT
Voltage Supply
Table
10–3:
chapter.
I/O power supply
PLL analog global power supply
PLL digital power supply
PLL differential clock input power supply (top and
bottom I/O banks only)
Battery back-up power supply for design security
volatile key storage
C CB AT
is 3.0-V.
Chapter 10: Hot Socketing and Power-On Reset in Stratix III Devices
Description
Table 10–2
RAMP
.
and
© March 2010 Altera Corporation
Table 10–3
Table
DC and Switching
Power-On Reset Specifications
1.2, 1.5, 1.8, 2.5, 3.0,
3.3
2.5
1.1
2.5
1.0 – 3.3
10–3.
Setting (V)
(1)
are required
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