EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 399
EP3SL150F1152C2N
Manufacturer Part Number
EP3SL150F1152C2N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C2N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2409
EP3SL150F1152C2NES
EP3SL150F1152C2NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3SL150F1152C2N
Manufacturer:
ALTERA
Quantity:
20 000
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IEEE Std. 1149.1 BST Architecture
© July 2010
SIII51013-1.9
Altera Corporation
f
f
This chapter discusses how to use the IEEE Std. 1149.1 boundary-scan test (BST)
circuitry in Stratix
efficiently components on PCBs with tight lead spacing. BST architecture tests pin
connections without using physical test probes and captures functional data while a
device is operating normally. Boundary-scan cells in a device can force signals onto
pins or capture data from pin or logic array signals. Forced test data is serially shifted
into the boundary-scan cells. Captured data is serially shifted out and externally
compared to expected results.
Figure 13–1. IEEE Std. 1149.1 Boundary-Scan Testing
In addition to BST, you can use the IEEE Std. 1149.1 controller for Stratix III device
in-circuit reconfiguration (ICR). However, this chapter only discusses the BST feature
of the IEEE Std. 1149.1 circuitry.
For information about configuring Stratix III devices by using the IEEE Std. 1149.1
circuitry, refer to the
Stratix III
A Stratix III device operating in IEEE Std. 1149.1 BST mode uses four required pins,
TDI, TDO, TMS, and TCK, and one optional pin, TRST. The TCK pin has an internal
weak pull-down resistor; the TDI, TMS, and TRST pins have weak internal pull-ups.
The TDO output pin and all of the JTAG input pins are powered by the
2.5-V/3.0-V/3.3-V V
during JTAG configuration.
For recommendations about how to connect a JTAG chain with multiple voltages
across the devices in the chain, refer to
page
13–17.
Devices, and the
Serial
Data In
®
III devices. The BST architecture offers the capability to test
JT
Configuring Stratix III
CCPD
Boundary-Scan Cell
AG Device 1
13. IEEE 1149.1 (JTAG) Boundary-Scan
Logic
Array
supply of I/O Bank 1A. All user I/O pins are tri-stated
Remote System Upgrades with Stratix III Devices
Figure 13–1
IC
Connection
“I/O Voltage Support in JTAG Chain” on
Pin Signal
Tested
Testing in Stratix III Devices
Devices,
shows the concept of BST.
Hot Socketing and Power-On Reset in
JTAG Device 2
Logic
Array
Stratix III Device Handbook, Volume 1
Serial
Data Out
chapters.
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