EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 57
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C2N
Manufacturer Part Number
EP3SL150F1152C2N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C2N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2409
EP3SL150F1152C2NES
EP3SL150F1152C2NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3SL150F1152C2N
Manufacturer:
ALTERA
Quantity:
20 000
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Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices
Adaptive Logic Modules
Figure 2–12. Conditional Operation Example
© February 2009 Altera Corporation
The equation for this example is:
R = (X < Y) ? Y : X
To implement this function, the adder is used to subtract Y from X. If X is less than Y,
the carry_out signal is 1. The carry_out signal is fed to an adder where it drives
out to the LAB local interconnect. It then feeds to the LAB-wide syncload signal.
When asserted, syncload selects the syncdata input. In this case, the data Y drives
the syncdata inputs to the registers. If X is greater than or equal to Y, the syncload
signal is de-asserted and X drives the data port of the registers.
The arithmetic mode also offers clock enable, counter enable, synchronous up/down
control, add/subtract control, synchronous clear, and synchronous load. The LAB
local interconnect data inputs generate the clock enable, counter enable, synchronous
up/down, and add/subtract control signals. These control signals are good
candidates for the inputs that are shared between the four LUTs in the ALM. The
synchronous clear and synchronous load options are LAB-wide signals that affect all
registers in the LAB. These signals can also be individually disabled or enabled per
register. The Quartus II software automatically places any registers that are not used
by the counter into other LABs.
Carry Chain
syncdata
X[0]
X[1]
X[2]
Y[0]
Y[1]
Y[2]
ALM 1
ALM 2
Comb &
Comb &
Comb &
Comb &
Adder
Adder
Adder
Adder
Logic
Logic
Logic
Logic
X[2]
X[1]
X[0]
Adder output
is not used.
syncload
syncload
syncload
D
D
D
reg0
reg1
reg0
carry_out
Q
Q
Q
R[0]
R[1]
R[2]
To general or
local routing
To general or
local routing
To general or
local routing
To local routing &
then to LAB-wide
syncload
Stratix III Device Handbook, Volume 1
2–13
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