EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 381
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C2N
Manufacturer Part Number
EP3SL150F1152C2N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C2N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2409
EP3SL150F1152C2NES
EP3SL150F1152C2NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3SL150F1152C2N
Manufacturer:
ALTERA
Quantity:
20 000
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Chapter 11: Configuring Stratix III Devices
Device Configuration Pins
Table 11–15. Optional Configuration Pins
© March 2011 Altera Corporation
CLKUSR
INIT_DONE
DEV_OE
DEV_CLRn
Pin Name
N/A if option is on. I/O
N/A if option is on. I/O
N/A if option is on. I/O
N/A if option is on. I/O
if option is off.
if option is off.
if option is off.
if option is off.
User Mode
Table 11–15
pins are not enabled in the Quartus II software, they are available as general-purpose
user I/O pins. Therefore, during configuration, these pins function as user I/O pins
and are tri-stated with weak pull-up resistors.
describes the optional configuration pins. If these optional configuration
Output open-drain
Pin Type
Input
Input
Input
Optional user-supplied clock input synchronizes the
initialization of one or more devices. Enable this pin by
turning on the Enable user-supplied start-up clock
(CLKUSR) option in the Quartus II software.
Use the Status pin to indicate when the device has
initialized and is in user mode. When nCONFIG is low and
during the beginning of configuration, the INIT_DONE
pin is tri-stated and pulled high due to an external 10-kΩ
INIT_DONE is programmed into the device (during the
first frame of configuration data), the INIT_DONE pin will
go low. When initialization is complete, the INIT_DONE
pin is released and pulled high and the device enters user
mode. Thus, the monitoring circuitry must be able to
detect a low-to-high transition. This pin is enabled by
turning on the Enable INIT_DONE output option in the
Quartus II software.
Optional pin that allows you to override all tri-states on the
device. When this pin is driven low, all I/O pins are
tri-stated, when this pin is driven high, all I/O pins behave
as programmed. Enable this pin by turning on the Enable
device-wide output enable (DEV_OE) option in the
Quartus II software.
Optional pin that allows you to override all clears on all
device registers. When this pin is driven low, all registers
are cleared. When this pin is driven high, all registers
behave as programmed. This pin is enabled by turning on
the Enable device-wide reset (DEV_CLRn) option in the
Quartus II software.
pull-up resistor. After the option bit to enable
Description
Stratix III Device Handbook, Volume 1
11–49
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