EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 238

IC STRATX III FPGA 150K 1152FBGA

EP3SL150F1152C2N

Manufacturer Part Number
EP3SL150F1152C2N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr

Specifications of EP3SL150F1152C2N

Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2409
EP3SL150F1152C2NES

Available stocks

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Manufacturer
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Part Number:
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Quantity:
10 000
Part Number:
EP3SL150F1152C2N
Manufacturer:
ALTERA
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Part Number:
EP3SL150F1152C2N
Manufacturer:
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Quantity:
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Part Number:
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Part Number:
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7–34
Figure 7–21. HSTL I/O Standard Termination for Stratix III Devices
Note to
(1) In Stratix III devices, you cannot use simultaneously series and parallel OCT. For more information, refer to
Differential I/O Standards Termination
Stratix III Device Handbook, Volume 1
Figure
External
On-Board
Termination
Termination
OCT
Receive
OCT
in Bi-
Directional
Pins (1)
OCT
Transmit
7–21:
1
Series OCT
50
Stratix III
Stratix III
Series OCT 50
Stratix III devices support differential SSTL-2 and SSTL-18, differential HSTL-18,
HSTL-15, HSTL-12, LVDS, LVPECL, RSDS, and mini-LVDS.
Figure 7–28
devices.
Differential HSTL and SSTL outputs are not true differential outputs. They use two
single-ended outputs with the second output programmed as inverted.
Transmitter
Transmitter
Transmitter
V CCIO
100
100
show the details of various differential I/O termination on Stratix III
HSTL Class I
50
50
50
50
V REF
V REF
50
50
V REF
V TT
V TT
V CCIO
Stratix III
V CCIO
100
100
100
100
Receiver
Receiver
Receiver
Stratix III
Parallel OCT
Series OCT
50
Series OCT
25
Stratix III
Stratix III
Series OCT 25
Transmitter
Transmitter
Transmitter
V CCIO
100
100
Chapter 7: Stratix III Device I/O Features
Termination Schemes for I/O Standards
V TT
V TT
HSTL Class II
V TT
“Dynamic OCT” on page
50
50
Figure 7–22
50
50 7
V REF
50
50
© July 2010 Altera Corporation
V REF
50
50
50
V REF
V TT
V TT
V CCIO
Stratix III
V CCIO
100
100
100
100
through
Receiver
Receiver
Receiver
Stratix III
Parallel OCT
Series OCT
25
7–25.

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