EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 449
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C2N
Manufacturer Part Number
EP3SL150F1152C2N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C2N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2409
EP3SL150F1152C2NES
EP3SL150F1152C2NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3SL150F1152C2N
Manufacturer:
ALTERA
Quantity:
20 000
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Chapter 16: Programmable Power and Temperature-Sensing Diodes in Stratix III Devices
Temperature Sensing Diode
Figure 16–1. Stratix III Power Management Example
Notes to
(1) When V
(2) When V
Temperature Sensing Diode
© February 2009 Altera Corporation
Figure
VIN
CCL
CCL
= 0.9 V, V
= 0.9 V, you need a separate voltage regulator.
16–1:
Voltage Regulator (V
Voltage Regulator (V
Voltage Regulator (V
CCPT
Voltage Regulator (Core)
Voltage Regulator (V
for the I/O Elements
Figure 16–1
Knowing the junction temperature is crucial for thermal management. A Stratix III
device monitors its die temperature with an embedded temperature sensing diode
(TSD). This is done by sensing the voltage level across the TSD. Each temperature
level produces a unique voltage across the diode. Use an external analog-to-digital
converter that measures the voltage difference across the TSD and then converts it to a
temperature reading.
Voltage Regulator
Voltage Regulator
Voltage Regulator
and V
Variable (1.1 V)
(Termination)
Fixed (2.5 V)
Fixed (2.5 V)
Fixed (1.1 V)
Fixed (2.5 V)
(V
(V
I/O (2.5 V)
CCA_PLL
CCPGM/
2.5 V
CC
must be ramped before V
)
)
CCPT
CCPD
shows an example of power management for Stratix III devices.
CCIO
CC
)
)
)
)
CCL
(Note
to minimize V
V
V
V
CCL
CC
CCIO
1),
V
CCPD
(2)
CCL
V
standby current during V
CCPGM
Stratix III
V
CCPT
V
CCA_PLL
CCPT
Stratix III Device Handbook, Volume 1
Reference
User I/O
Voltage
V
and V
REF
CC
ramping to full rail.
Termination
Resistor
16–5
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