EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 317
EP3SL150F1152C2N
Manufacturer Part Number
EP3SL150F1152C2N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C2N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2409
EP3SL150F1152C2NES
EP3SL150F1152C2NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3SL150F1152C2N
Manufacturer:
ALTERA
Quantity:
20 000
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Chapter 9: High-Speed Differential I/O Interfaces and DPA in Stratix III Devices
Differential Pin Placement Guidelines
Guidelines for DPA-Disabled Differential Channels
© July 2010
Altera Corporation
When DPA-disabled channels are used in the left and right banks of a Stratix III
device, you must adhere to the guidelines in the following sections.
DPA-Disabled Channels and Single-Ended I/Os
The placement rules for DPA-disabled channels and single-ended I/Os are the same
as those for DPA-enabled channels and single-ended I/Os.
DPA-Disabled Channel Driving Distance
Each left/right PLL can drive all the DPA-disabled channels in the entire bank.
Using Corner and Center Left/Right PLLs
A corner left/right PLL can be used to drive all transmitter channels and a center
left/right PLL can be used to drive all DPA-disabled receiver channels within the
same differential bank. In other words, a transmitter channel and a receiver channel in
the same LAB row can be driven by two different PLLs, as shown in
A corner left/right PLL and a center left/right PLL can drive duplex channels in the
same differential bank as long as the channels driven by each PLL are not interleaved.
No separation is necessary between the group of channels driven by the corner and
center left/right PLLs. Refer to
Figure 9–21
and
Figure
9–22.
Stratix III Device Handbook, Volume 1
Figure
9–21.
9–23
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