EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 187
EP3SL150F1152C2N
Manufacturer Part Number
EP3SL150F1152C2N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C2N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2409
EP3SL150F1152C2NES
EP3SL150F1152C2NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3SL150F1152C2N
Manufacturer:
ALTERA
Quantity:
20 000
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Chapter 6: Clock Networks and PLLs in Stratix III Devices
PLLs in Stratix III Devices
Programmable Bandwidth
Figure 6–37. Open- and Closed-Loop Response Bode Plots
© July 2010
Altera Corporation
Open-Loop Reponse Bode Plot
Closed-Loop Reponse Bode Plot
Gain
Gain
0 dB
Stratix III PLLs provide advanced control of the PLL bandwidth using the PLL loop's
programmable characteristics, including loop filter and charge pump.
Background
PLL bandwidth is the measure of the PLL's ability to track the input clock and its
associated jitter. The closed-loop gain 3-dB frequency in the PLL determines the PLL
bandwidth. The bandwidth is approximately the unity gain point for open loop PLL
response. As
frequency. Stratix III PLLs provide three bandwidth settings—low, medium (default),
and high.
Figure 6–37
shows, these points correspond to approximately the same
Frequency
Frequency
Increasing the PLL's
bandwidth in effect pushes
the open loop response out.
Stratix III Device Handbook, Volume 1
6–39
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