EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 220

• Manufacturer Part Number: EP3SL150F1152C2N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C2N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2409; EP3SL150F1152C2NES

7–16
Programmable Slew Rate Control
Stratix III Device Handbook, Volume 1
1
Table 7–5. Programmable Current Strength
Altera recommends performing IBIS or SPICE simulations to determine the right
current strength setting for your specific application.
The output buffer for each Stratix III device regular- and dual-function I/O pin has a
programmable output slew-rate control that you can configure for low-noise or
high-speed performance. A faster slew rate provides high-speed transitions for
high-performance systems. A slow slew rate can help reduce system noise, but adds a
nominal delay to rising and falling edges. Each I/O pin has an individual slew-rate
control, allowing you to specify the slew rate on a pin-by-pin basis.
You cannot use the programmable slew rate feature when using OCT R
The Quartus II software allows four settings for programmable slew rate control—0,
1, 2, and 3—where 0 is slow slew rate and 3 is fast slew rate.
setting for the I/O standards supported in the Quartus II software.
3.3-V LVTTL
3.3-V LVCMOS
3.0-V LVTTL
3.0-V LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVTTL/LVCMOS
1.2-V LVTTL/LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-15 Class I
SSTL-15 Class II
HSTL-18 Class I
HSTL-18 Class II
HSTL-15 Class I
HSTL-15 Class II
HSTL-12 Class I
HSTL-12 Class II
Note to
(1) The default setting in the Quartus II software is 50-Ω OCT R
HSTL/SSTL class I I/O standards. The default setting is 25-Ω OCT R
I/O standards.
Table
I/O Standard
7–5:
I
O H
/ I
12, 10, 8, 6, 4, 2
12, 10, 8, 6, 4, 2
Setting (mA) for
Column I/O Pins
OL
12, 10, 8, 6, 4
12, 10, 8, 6, 4
12, 10, 8, 6, 4
12, 10, 8, 6, 4
12, 10, 8, 6, 4
16, 12, 8, 4
16, 12, 8, 4
16, 12, 8, 4
16, 12, 8, 4
16, 12, 8, 4
Current Strength
8, 6, 4, 2
12, 10, 8
(Note 1)
16, 8
16, 8
16
16
16
16
S
without calibration for all non-voltage reference and
S
without calibration for HSTL/SSTL class II
Chapter 7: Stratix III Device I/O Features
Table 7–6
I
O H
© July 2010 Altera Corporation
/ I
Setting (mA) for
OL
12, 10, 8, 6, 4
12, 10, 8, 6, 4
Row I/O Pins
Current Strength
8, 6, 4, 2
8, 6, 4, 2
12, 8, 4
12, 8, 4
12, 8, 4
8, 6, 4
8, 6, 4
8, 6, 4
12, 8
16, 8
Stratix III I/O Structure
8, 4
8, 4
4, 2
lists the default
16
—
16
—
—
S
.