IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 102

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
3.23.3
20~3FH / b2, T1/J1-TPLC-indirect registers-10~18H) (the PCCE [b0,
E1-060H / b0, T1/J1-030H] in the TPLC must be logic 1), each framer
can be set in the Payload Loopback mode. When the Receive Clock
Master modes are enabled, the Elastic Store is used to align the line
received data to the frame to be transmitted. When the Receive Clock
Slave modes are enabled, the Elastic Store is unavailable to implement
Functional Description
TSCCKA
TSCCKB/
MTSCCKB
TSCFS/
MTSCFS
MTSSIG[1:2]
MTSD[1:2]
RSCCK/
MRSCCK
RSCFS/
MRSCFS
MRSD[1:2]
MRSSIG[1:2]
MRSFS[1:2]
By programming the LOOP (b2, E1-TPLC-indirect registers-
PAYLOAD LOOPBACK
TSDn
TSFSn/
TSSIGn
RSDn
RSCKn/
RSSIGn
RSFSn
Generator
/Detector
Transmit
Interface
Interface
PRBS
Receive
System
System
Payload
Receive
Control
Loopback
Figure 72. Payload Loopback
Payload
Transmit
Payload
Control
One of the Eight Framers
92
CAS/RBS
Transmitter
Receive
Buffer
the payload loopbacks, and loopback functionality is provided only when
the Transmit System Interfaces are also in a Transmit Clock Slave
mode, and the received and transmitting clocks and frame alignment are
identical (RSCCK = TSCCKB, RSCFS = TSCFS). Thus, the selected
time slot/channel in the transmit path will be overwritten by the corre-
sponding received time slot/channel. The remaining time slots/channels
in the transmit path are intact. Figure 72 shows the process.
HDLC
#1
Frame Generator
#2 #3
Elastic
Detector
Buffer
Bit-Oriented
Store
Alarm
Message
Receiver
Loopback
Generator
Inband
Code
Frame Processor
Receiver #1
Performance
Monitor
HDLC
Bit-Oriented
Transmitter
Message
Transmit
Loopback
Clock
Detector
Inband
Code
#2 #3
T1 / E1 / J1 OCTAL FRAMER
Attenuator
Transmit
Jitter
Attenuator
Receive
Jitter
March 5, 2009
LTCKn
LRCKn
LTDn
LRDn
XCK