IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 257

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
T1 / J1 FRMG Configuration (044H, 0C4H, 144H, 1C4H, 244H, 2C4H, 344H, 3C4H)
MTRK:
channels with the data on the TSSIGn/MTSSIG pin or the data in the A, B, C, D (b3~0, T1/J1-TPLC-indirect registers-31~48H) according to the setting
in the SIGC[1:0] (b7~6, T1/J1-TPLC-indirect registers-31~48H).
J1_CRC:
J1_YEL:
ESF:
GZCS[1:0]:
01~18H).
Programming Information
Bit Name
Default
Bit No.
Type
Valid when the PCCE (b0, T1/J1-030H) is logic 1.
= 0: Normal operation.
= 1: Replace the data on all channels with the data set in the IDLE[7:0] (b7~0, T1/J1-TPLC-indirect registers-19~30H); replace the signaling on all
This bit selects the T1 or J1 CRC-6 algorithm when the ESF (b4, T1/J1-044H) is ‘1’.
= 0: The CRC-6 algorithm meets T1 standard.
= 1: The CRC-6 algorithm meets J1 standard.
This bit selects the T1 or J1 Yellow alarm pattern to be transmitted.
= 0: The Yellow alarm transition meets T1 standard.
= 1: The Yellow alarm transition meets J1 standard.
The Yellow alarm pattern is:
- In T1 SF format: Transmit logic 0 on the 2nd bit of each channel.
- In T1 ESF format: Transmit ‘FF00’ on each FDL link.
- In J1 SF format: Transmit logic 1 on the 12th F-bit.
- In J1 ESF format: Transmit ‘FFFF’ on each FDL link.
The SF or ESF format is selected by the ESF (b4, T1/J1-044H).
This bit selects the SF or ESF format in the Frame Generator block.
= 0: The SF format is selected.
= 1: The ESF format is selected.
These bits select the Zero Code Suppression format to be used. They are logically ORed with the ZCS[1:0] (b1~0, T1/J1-TPLC-indirect registers-
GZCS[1:0]
0 0
0 1
1 0
1 1
MTRK
R/W
7
0
No zero code suppression.
GTE Zero Code Suppression - Every bit 8 (or bit 7 in signaling frames) is forced to be logic one when the bits in a channel are all ‘Zero’s.
Reserved.
Bell Zero Code Suppression - Every bit 7 is forced to be logic one when the bits in a channel are all ‘Zero’s.
J1_CRC
R/W
6
0
J1_YEL
R/W
5
0
ESF
R/W
4
0
Zero Code Suppression
247
3
Reserved
2
T1 / E1 / J1 OCTAL FRAMER
GZCS[1]
R/W
1
0
March 5, 2009
GZCS[0]
R/W
0
0