IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 66

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
071H]);
07EH & b7~0, E1-07FH) are updated.
SYNCE (b7, E1-071H) and XFERE (b5, E1-071H) respectively, the INT
pin is asserted.
3.12.2
the eight framers can be linked to pattern generator or detector by the
PRGDSEL[2:0] (b7~5, T1/J1-00FH). The pattern can be inserted in
either the transmit or receive direction, and detected in the opposite
direction. The direction is determined by the RXPATGEN (b2, T1/J1-
00FH). The pattern can be generated and detected in unframed or
framed mode. The selection is made by the UNF_GEN (b1, T1/J1-00FH)
and UNF_DET (b0, T1/J1-00FH) respectively. In unframed mode, all 24
channels are replaced or extracted and the specification in the TEST
(b3, T1/J1-RPLC-indirect registers - 01~18H or b3, T1/J1-TPLC-indirect
registers - 01~18H) in Receive / Transmit Payload Control blocks is
ignored. In framed mode, the channel is specified by the TEST (b3, T1/
J1-RPLC-indirect registers - 01~18H or b3, T1/J1-TPLC-indirect regis-
ters - 01~18H). However, fractional T1/J1 signal will be replaced or
extracted in the specified channel when the Nx56k_GEN (b4, T1/J1-
00FH) or Nx56k_DET (b3, T1/J1-00FH) is set respectively.
3.12.2.1
J1-060H) is located in the PI[31:0] (b7~0, T1/J1-068H & b7~0, T1/J1-
069H & b7~0, T1/J1-06AH & b7~0, T1/J1-06BH). However, the length of
the valid data in the PI[31:0] is determined by the PL[4:0] (b4~0, T1/J1-
062H). If the repetitive pattern is chosen, the valid PI[X:0] (‘X’ is valid for
1 to 31) reflect its content directly. If the pseudo-random pattern is cho-
sen, the valid PI[X:0] are its initial value and the feedback tap position
(refer to Figure 36) is determined by the PT[4:0] (b4~0, T1/J1-063H). A
single bit error will be inserted by setting the EVENT (b3, T1/J1-064H),
or continuous bit errors will be inserted at a bit error rate determined by
the EIR[2:0] (b2~0, T1/J1-064H). Before replacing the data in the
assigned direction, the pattern can be inverted by setting the TINV (b3,
T1/J1-060H).
3.12.2.2
repetitive or pseudo-random pattern, as chosen by the PS (b4, T1/J1-
060H). Before being compared, the data can be inverted by setting the
RINV (b2, T1/J1-060H). The extracted data is then compared with a 48-
bit fixed window loaded with the pattern. This process continues until the
data coincides with the pattern. They are then synchronized with an indi-
cation in the SYNCV (b4, T1/J1-061H). Bit errors in the synchronized
data are indicated in the BEI (b2, T1/J1-061H). When there are more
than 10-bit errors in the fixed 48-bit window, the extracted data is out of
synchronization. Automatic search for the re-synch will be done with the
Functional Description
3 kinds of interrupts can be generated by this block:
- bit errors;
- synchronization status change (indicated in the SYNCI [b3, E1-
- the PD[31:0] (b7~0, E1-07CH & b7~0, E1-07DH & b7~0, E1-
When the interrupts are enabled by the BEE (b6, E1-071H),
The PRBS Generator/Detector is a global control block. Any one of
The repetitive or pseudo-random pattern chosen by the PS (b4, T1/
The extracted data from the assigned direction is compared with a
T1/J1 MODE
Pattern Detector
Pattern Generator
56
AUTOSYNC (b1, T1/J1-060H) configured, or manual search will be
done when there is a transition from low to high on the MANSYNC (b0,
T1/J1-060H). A manual search is recommended to execute to ensure
the PRGD operates correctly when there is any setting change of the
PRGD registers or the detector data source changes.
T1/J1-06CH & b7~0, T1/J1-06DH & b7~0, T1/J1-06EH & b7~0, T1/J1-
06FH) can contain the received pattern, the total error count or the total
number of received bits. They update when the defined intervals are ini-
tiated. The intervals equal 1 second when the AUTOUPDATE (b0, T1/
J1-000H) is set in the corresponding framer. They can also be updated
by writing to any of the PD[31:0] (b7~0, T1/J1-06CH & b7~0, T1/J1-
06DH & b7~0, T1/J1-06EH & b7~0, T1/J1-06FH), or to the T1/J1 Chip
ID / Global PMON Update register (T1/J1-00CH). The update will be
indicated by the XFERI (b1, T1/J1-061H). If they are not read in the
defined intervals, the PD[31:0] (b7~0, T1/J1-06CH & b7~0, T1/J1-06DH
& b7~0, T1/J1-06EH & b7~0, T1/J1-06FH) will be overwritten with new
data. The overwritten condition is indicated by the OVR (b0, T1/J1-
061H).
061H]);
J1-06EH & b7~0, T1/J1-06FH) are updated.
SYNCE (b7, T1/J1-061H) and XFERE (b5, T1/J1-061H) respectively,
the INT pin is asserted.
Selected by the PDR[1:0] (b7~6, T1/J1-060H), the PD[31:0] (b7~0,
3 kinds of interrupts can be generated by this block:
- bit errors;
- synchronization status change (indicated in the SYNCI [b3, T1/J1-
- the PD[31:0] (b7~0, T1/J1-06CH & b7~0, T1/J1-06DH & b7~0, T1/
When the interrupts are enabled by the BEE (b6, T1/J1-061H)
T1 / E1 / J1 OCTAL FRAMER
March 5, 2009