IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 256

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
T1 / J1 RCRB Signaling State Change Channels 1-8 (COSS = 1) (043H, 0C3H, 143H, 1C3H, 243H, 2C3H, 343H, 3C3H)
COSSn:
T1 / J1 RCRB Channel Signaling Data Registers (COSS = 0) (RCRB Indirect Registers 01H ~ 18H / 21H ~ 38H)
A, B, C, D:
B, C, D code in the corresponding indirect registers 21H ~ 38H. To avoid this 2 ms delay, users can read the corresponding b3~0 in the indirect regis-
ters 01H ~ 18H first. If the value of these four bits are different from the previous A, B, C, D code, then the content of b3~0 in the 01H ~ 18H is the
updated A, B, C, D code. If the content of the four bits is the same as the previous A, B, C, D code, then users should read the b3~0 in the 21H ~ 38H
to get the updated A, B, C, D code.
T1 / J1 RCRB Per-Channel Configuration Registers (COSS = 0) (RCRB Indirect Registers 41H ~ 58H)
DEB:
of a channel are the same.
Programming Information
Bit Name
Bit Name
Bit Name
Default
Default
Bit No.
Default
Bit No.
Bit No.
Type
Type
= 0: The signaling in its corresponding channel is not changed.
= 1: The signaling in its corresponding channel is changed.
These bits are cleared to ‘0’ after the register is read. COSS[8:1] correspond to channels 8 to 1.
Type
They contain the signaling of the corresponding channel.
There is a maximum 2 ms delay between the transition of the COSS[n] bit (T1/J1-041H & T1/J1-042H & T1/J1-043H) and the updating of the A,
In SF format, the C and D are the repetition of the A and B respectively.
= 0: Disable signaling debounce.
= 1: Enable signaling debounce (valid only if the PCCE is logic 1). That is, the signaling is acknowledged only when 2 consecutive signaling bits
COSS[8]
R
X
7
7
7
01H ~ 18H / 21H ~ 38H
19H ~ 20H, 39H ~ 40H
COSS[7]
41H ~ 58H
R
6
X
6
6
Reserved
COSS[6]
R
X
5
5
5
RCRB Indirect Registers Map
COSS[5]
Per-Channel Configuration Register for Channel 1 ~ 24
Reserved
Channel Signaling Data Register for Channel 1 ~ 24
R
X
4
4
4
246
COSS[4]
R
X
A
R
X
3
3
3
-
COSS[3]
R
B
R
X
2
X
2
2
T1 / E1 / J1 OCTAL FRAMER
COSS[2]
C
R
X
R
X
1
1
1
March 5, 2009
COSS[1]
DEB
R/W
D
R
X
R
X
0
X
0
0