IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 189

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
E1 FRMG National Bit Codeword (047H, 0C7H, 147H, 1C7H, 247H, 2C7H, 347H, 3C7H)
SaX_ENn:
SaX[1:4]:
word is written during SMF II of a Multi-Frame, its contents will be latched internally and will appear in SMF I of the next Multi-Frame.
E1 RHDLC #1, #2, #3 Configuration (048H, 0C8H, 148H, 1C8H, 248H, 2C8H, 348H, 3C8H)
E1-00AH).
MEN, MM:
TR:
new HDLC search.
EN:
Programming Information
Bit Name
Bit Name
Default
Default
Bit No.
Bit No.
Type
Type
Valid when the FDIS (b3, E1-040H) is logic 0, and the INDIS (b1, E1-040H) is logic 0.
= 0: Disable the corresponding bit in the SaX[1:4] to replace the national bit codeword selected by the SaSEL[2:0].
= 1: Enable the corresponding bit in the SaX[1:4] to replace the national bit codeword selected by the SaSEL[2:0].
These bits are the codeword to be inserted into a CRC-4 Sub Multi-Frame.
The setting in the SaX[1:4] will replace the National bits which are assigned by the SaSEL[2:0].
If the code word is written during SMF I of a CRC-4 Multi-Frame, it will appear in the SaX[1:4] bits of SMF II of the same Multi-Frame. If the code
Selection of the RHDLC block (#1, #2, or #3) whose registers are visible on the microprocessor interface is done via the RHDLCSEL[1:0] (b7~6,
The MEN & MM define the address matching mode:
MEN
= 0: Normal operation.
= 1: Force the RHDLC to immediately terminate the reception of the current data frame, empty the FIFO buffer, clear the interrupts and initiate a
This bit is clear to ‘0’ after a rising and falling edge occur on the internal clock or after the register is read.
= 0: Disable the operation of the RHDLC block and all the FIFO buffer and interrupts are cleared.
= 1: Enable the operation of the RHDLC block and the HDLC opening flag will be searched immediately.
0
1
1
SaX_EN[1]
R/W
MM
X
7
0
7
0
1
No address matching is needed. All the HDLC data is stored in the FIFO.
The HDLC data is stored in the FIFO when the first byte is all ‘One’s or the same as the setting in the PA[7:0] (b7~0, E1-04CH) or
the SA[7:0] (b7~0, E1-04DH).
The HDLC data is stored in the FIFO when the most significant 6 bits in the first byte are all ‘One’s or the same as the setting in the
PA[7:2] (b7~2, E1-04CH)or the SA[7:2] (b7~2, E1-04DH).
SaX_EN[2]
R/W
6
0
6
Reserved
SaX_EN[3]
R/W
5
0
5
SaX_EN[4]
R/W
4
0
4
179
Address Matching Mode
SaX[1]
MEN
R/W
R/W
3
1
3
0
SaX[2]
R/W
R/W
MM
2
1
2
0
T1 / E1 / J1 OCTAL FRAMER
SaX[3]
R/W
R/W
TR
1
1
1
0
March 5, 2009
SaX[4]
R/W
R/W
EN
0
1
0
0