IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 50

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
When it is for framing pulse indication, the valid polarity of MRSFS is
configured by the FPINV (b6, E1-011H). The FPINV (b6, E1-011H) of the
eight framers should be set to the same value.
naling. The extracted signaling bits are time slot aligned with the data
output on MRSD. In the Out of Signaling Multi-Frame condition, the out-
Functional Description
MRSCCK
MRSSIG
MRSCCK
MRSFS
MRSSIG
MRSCFS
MRSCFS
MRSFS
MRSD
MRSD
When the TSOFF[6:0] of Framer1 are set to 7'b0000000, the TSOFF[6:0] of Framer2 are set to 7'b0000001, the TSOFF[6:0] of Framer3 are set to 7'b0000010, the TSOFF[6:0] of Framer4 are set to 7'b0000011,
the BOFF_EN of the four Framers are set to logic 0:
When the TSOFF[6:0] of Framer1 are set to 7'b0000000, the TSOFF[6:0] of Framer2 are set to 7'b0000001, the TSOFF[6:0] of Framer3 are set to 7'b0000010, the TSOFF[6:0] of Framer4 are set to 7'b0000011,
the BOFF_EN of the four Framers are set to logic 0:
In the Receive Multiplexed mode, MRSSIG outputs extracted sig-
C
7
C
7
D
8
D
8
X
1
X
1
X
2
2
X
3
X
Framer1_TS0
3
X
X
4
Framer1_TS0
X
4
Figure 20. E1 Receive Multiplexed Mode - Functional Timing Example 1
Figure 21. E1 Receive Multiplexed Mode - Functional Timing Example 2
A
5
A
5
6
B
6
B
7
C
C
7
8
D
8
D
In this example, Framer1 to Framer4 are supposed to be multiplexed to one multiplexed bus.
X
1
In this example, Framer1 to Framer4 are supposed to be multiplexed to one multiplexed bus.
X
1
X
2
X
2
Framer2_TS0
The CMS (b2, E1-010H) is logic 0, i.e., the bankplane rate is 8.192Mbit/s.
The CMS (b2, E1-010H) is logic 1, i.e., the bankplane rate is 16.384Mbit/s.
3
X
The DE (b4, E1-010H) is logic 1 and the FE (b3, E1-010H) is logic 0.
3
X
The DE (b4, E1-010H) is logic 0 and the FE (b3, E1-010H) is logic 0.
Framer2_TS0
X
4
X
4
5
A
5
A
6
B
6
B
C
7
C
7
8
D
8
D
X
1
X
1
X
2
X
2
40
3
X
Framer3_TS0
3
X
put signaling ABCD on the MRSSIG pin will be forced to be all ones if
the OOSMFAIS (b2, E1-001H) is set.
each time slot is the first bit to be output.
X
4
X
4
Framer3_TS0
A
5
Figure 20 & Figure 21 show the functional timing examples. Bit 1 of
A
5
6
B
6
B
7
C
7
C
8
D
8
D
X
1
X
1
X
2
X
2
3
X
Framer4_TS0
3
X
X
4
X
4
Framer4_TS0
5
A
(The 'X' represent the filled bits and has no meaning.)
5
A
(The 'X' represent the filled bits and has no meaning.)
6
B
6
B
7
C
T1 / E1 / J1 OCTAL FRAMER
7
C
8
D
8
D
1
X
X
1
2
X
X
2
3
X
3
X
Framer1_TS1
4
X
4
X
March 5, 2009
A
Framer1_TS1
5
A
5
6
B
6
B
7
C
7
C
8
D
8
D