IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 120

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
Table 52: Various Operation Modes in Receive Path for Reference (Continued)
Operation
Receive Clock
Receive Multi-
plexed Mode
Master Frac-
tional T1/J1
Mode
Mode
Indirect Registers)
01H-18H (RPLC
Register
02CH
001H
003H
020H
040H
050H
001H
081H
101H
181H
201H
281H
301H
381H
003H
083H
103H
183H
203H
283H
303H
383H
077H
0F7H
177H
1F7H
277H
2F7H
377H
3F7H
020H
0A0H
120H
1A0H
220H
2A0H
320H
3A0H
1
Value (from Bit7 to Bit0)
00000000
00010000
00110000
00010000
00000100
00000001
01000000
11001000
11001000
11001000
11001000
11001000
11001000
11001000
11001000
01010011
01010011
01010011
01010011
00000000
00000001
00000010
00000011
00000000
00000001
00000010
00000011
00110000
00110000
00110000
00110000
00110000
00110000
00110000
00110000
11010011
11010011
11010011
11010011
In the Receive Clock Master Nx64k mode.
Enable the normal operation of the RSDn pin. The data on RSDn and RSFSn is updated on the
rising edge of RSCK.
The Frame Processor is set in the ESF format. The CRC-6 calculation is performed when mimic
framing pattern is present
The Alarm Detector is set in the ESF format.
The Receive CAS/RBS Buffer is set in the ESF format.
Enable the Receive Payload Control.
The code in the DTRK[7:0] replaces the data output on the RSDn pin in the corresponding chan-
nel.
In the Receive Multiplexed mode. The receive backplane rate is 8.192 Mbit/s.
Multiplex the data stream of these four framers to the multiplexed bus 1. Enable the normal
operation of the MRSD and MRSSIG pins.The data on MRSD and MRSSIG is updated on the
rising edge of MRSCCK. The data on MRSCFS is sampled on the falling edge of MRSCCK.
Multiplex the data stream of these four framers to the multiplexed bus 2. Enable the normal
operation of the MRSD and MRSSIG pins.The data on MRSD and MRSSIG is updated on the
rising edge of MRSCCK. The data on MRSCFS is sampled on the falling edge of MRSCCK.
TSOFF[6:0] = 0. The time slot offset is 0.
TSOFF[6:0] = 1. The time slot offset is 1.
TSOFF[6:0] = 2. The time slot offset is 2.
TSOFF[6:0] = 3. The time slot offset is 3.
TSOFF[6:0] = 0. The time slot offset is 0.
TSOFF[6:0] = 1. The time slot offset is 1.
TSOFF[6:0] = 2. The time slot offset is 2.
TSOFF[6:0] = 3. The time slot offset is 3.
The Frame Processor is set in the ESF format. The CRC-6 calculation is performed when mimic
framing pattern is present.
110
Description
2
T1 / E1 / J1 OCTAL FRAMER
March 5, 2009