IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 90

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
Table 36: Remote Alarm Indication
Frame 13 & 15 (E1 & E2 bits) are used for FEBE indication only if the
FEBEDIS (b2, E1-040H) is logic 0. When there are CRC calculated
errors in SMF I or SMF II in the received data stream, a logic 0 will be
automatically replaced in the E1 or the E2 bit for indication respectively.
When the received data is out of CRC-4 Multi-Frame synchronization,
the E1 and E2 bits can be forced to be logic 0 or logic 1, as determined
by the OOCMFE0 (b1, E1-00EH).
frame 0 (Y bit) is for Signaling Multi-Frame Alarm Indication. A logic 1 in
the Y bit means the Signaling Multi-Frame Alarm. However, the value of
the corresponding SaX_EN[1:4] (b7~4, E1-047H), it will replace the data
on the National bits whose position is selected by the SaSEL[2:0] (b7~5,
E1-046H).
7 in TS16 of Frame 0 of the Signaling Multi-Frame) will be replaced with
the setting in the X[2:0] (b0~1 & b3, E1-043H) if the XDIS (b0, E1-040H)
is logic 0.
3.15.1.4
cuted:
‘0011011’ to ‘1100100’ by setting the FPATINV (b6, E1-041H);
inverted from ‘1’ to ‘0’ by setting the SPLRINV (b5, E1-041H);
Functional Description
Table 37: Content in International Bits (when the INDIS [b1, E1-040H] is logic 0)
REMAIS(b3, E1-041H) AUTOYELLOW(b3, E1-000H) G706RAI(b0, E1-00EH)
GENCRC(b4, E1-040H) FEBEDIS(b2, E1-040H)
When CRC-4 Multi-Frame is generated, the International bits of
When Signaling Multi-Frame is generated, the 6th bit of TS16 of
When the setting in the SaX[1:4] (b3~0, E1-047H) is activated by
When Signaling Multi-Frame is generated, the extra bits (bits 4, 6 &
For diagnostic purposes, three kinds of data inversion can be exe-
1. When Basic Frame is generated, the FAS can be inverted from
2. When Basic Frame is generated, the 2nd bit of the NFAS can be
1
0
0
0
1
1
Diagnostics
0
1
-
1
0
-
The international bits of the FAS frame represent the setting in the Si[1] (b7, E1-042H), while the international bits
of the NFAS frame represent the setting in the Si[0] (b6, E1-042H).
The international bits of the FAS frame represent the calculated CRC-4 bits; the international bits of the former six
NFAS frames represent the CRC-4 alignment sequence (001011). The other two international bits in Frame 13 &
15 represent whether there are CRC-4 calculated errors in the received data stream (FEBE).
The international bits of the FAS frame represent the calculated CRC-4 bits; the international bits of the former six
NFAS frames represent the CRC-4 alignment sequence (001011). The other two international bits in Frame 13 &
15 represent the setting in the Si[1:0] (b7~6, E1-042H) respectively.
0
1
-
-
80
Manually force the remote alarm indication signal to be logic 1.
(per ETSI) The RAI is transmitted when any of the four conditions occurs in the
received data stream: 1. out of Basic Frame; 2. during AISD; 3. in CRC-4 to non-
CRC-4 interworking; 4. the offline searching is out of Basic Frame synchronization.
(per Annex B of G.706) The RAI is transmitted when any of the two conditions
occurs in the received data stream: 1. out of Basic Frame; 2. during AISD.
The RAI is not transmitted, that is, logic 0 is forced to transmit in its position.
the Y bit can be forced to be logic 0 or logic 1 by the MFAIS (b2, E1-
041H).
3.15.1.3
bit in TS0) can be replaced when the INDIS (b1, E1-040H) is logic 0.
and FEBE signal can all replace the International bits. Their priorities are
controlled by the GENCRC (b4, E1-040H) and the FEBEDIS (b2, E1-
040H) and illustrated in Table 37.
Frame alignment pattern can be inverted from ‘0000’ to ‘1111’ by setting
the SPATINV (b4, E1-041H).
All ones will be transmitted only in TS16 when the TS16AIS (b1, E1-
041H) is set. All ones will also be transmitted on all the time slots when
the AIS (b0, E1-041H) is set.
stream to be transmitted. The FIFO can be initiated by setting the
FRESH (b7, E1-040H).
3.15.1.5
tions are met, the corresponding Interrupt Status bit will be logic 1. Then
the interrupt will occur on the INT pin if the Interrupt Enable bit is logic 1.
After the Basic Frame is generated, the International bits (the first
The setting in the Si[1:0] (b7~6, E1-042H), the CRC-4 Multi-Frame
3. When Signaling Multi-Frame is generated, the Signaling Multi-
Of all the operations, transmitting all ones take the highest priority.
A FIFO is employed in the Frame Generator to store the data
The interrupt sources are summarized in Table 38. When the condi-
Data on the International Bits
Control Over International / National / Extra Bits
Interrupt Summary
Remote Alarm Indication Signal
T1 / E1 / J1 OCTAL FRAMER
March 5, 2009