IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 20

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
Pin Description
VDDC[5:12]
GNDIO[0]
GNDIO[1]
GNDIO[2]
GNDIO[3]
VDDIO[0]
VDDIO[1]
VDDIO[2]
VDDIO[3]
VDDC[0]
VDDC[1]
VDDC[2]
VDDC[3]
VDDC[4]
Name
TRST
BIAS
TMS
TDO
TCK
TDI
Tri-State
Ground
Power
Power
Power
Type
Input
Input
Input
Input
PQFP PBGA
125
128
126
127
124
107
116
17
18
49
74
20
51
85
92
19
50
75
30
-
Pin No.
D10
K12
F11
G4
G1
M6
D5
B3
A3
D4
C4
A6
C8
E8
E7
E6
E5
K1
E9
F1
J7
L6
F8
F7
F6
F5
F2
TRST: Test Reset (Active Low)
A low signal on this pin will reset the JTAG test port anytime. This pin is a Schmitt-triggered input with an internal
pull-up resistor. It must be connected to the RST pin or ground when JTAG is not used.
TMS: Test Mode Select
The signal on this pin controls the JTAG test performance and is clocked into the device on the rising edge of the
TCK. This pin has an internal pull-up resistor.
TCK: Test Clock
The clock for the JTAG test is input on this pin. The TDI and the TMS are clocked into the device on the rising edge
of the TCK and the TDO is clocked out of the device on the falling edge of the TCK.
TDI: Test Input
The test data are input on this pin. It is sampled on the rising edge of the TCK. This pin has an internal pull-up resis-
tor.
TDO: Test Output
The test data are output on this pin. It is sampled on the falling edge of the TCK. This pin is in tri-state mode, except
during the process of scanning of the data.
BIAS: +5V Bias
This pin enables +5 V tolerance on the inputs. When +5 V tolerance inputs are required, the BIAS must be con-
nected to a well-decoupled +5 V rail. When +3 V input is required, the BIAS must be connected to a well-decoupled
+3.3 V DC supply.
During power up, the BIAS pin should be powered no later than any VDDC/VDDIO pin is powered.
VDDIO[3:0]:
These pins must be connected to a common, well-decoupled +3.3 V DC supply together with the core power pins
VDDC[4:0] externally.
VDDC[4:0]:
These pins must be connected to a common, well-decoupled +3.3 V DC supply together with the pad ring power
pins VDDIO[3:0] externally.
The VDDC[5:12] are extra power pins for PBGA.
GNDIO[3:0]:
These pins must be connected to a common ground together with the core ground pins GNDC[4:0].
Power & Ground
10
Description
T1 / E1 / J1 OCTAL FRAMER
March 5, 2009