IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 16

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
2
Pin Description
RSCK[1] / RSSIG[1] /
RSCK[2] / RSSIG[2] /
RSCK[3] / RSSIG[3]
RSCK[4] / RSSIG[4]
RSCK[5] / RSSIG[5]
RSCK[6] / RSSIG[6]
RSCK[7] / RSSIG[7]
RSCK[8] / RSSIG[8]
RSD[1] / MRSD[1]
RSD[2] / MRSD[2]
MRSSIG[1]
MRSSIG[2]
LRCK[1]
LRCK[2]
LRCK[3]
LRCK[4]
LRCK[5]
LRCK[6]
LRCK[7]
LRCK[8]
RSD[3]
RSD[4]
RSD[5]
RSD[6]
RSD[7]
RSD[8]
LRD[1]
LRD[2]
LRD[3]
LRD[4]
LRD[5]
LRD[6]
LRD[7]
LRD[8]
Name
PIN DESCRIPTION
Output
Output
Type
Input
Input
PQFP PBGA
31
33
35
37
32
34
36
38
96
91
88
83
80
77
72
69
97
94
89
84
81
78
73
70
1
3
5
7
2
4
6
8
Pin No.
D12
G11
M12
C12
G10
C11
E12
H11
B12
E10
F12
K11
J11
M1
G9
A2
B2
A1
B1
C3
D3
C2
E4
K2
K3
K4
H9
F9
J4
L1
L2
L3
LRD[1:8]: Line Receive Data for Framer 1 ~ 8
These pins receive the data stream from line interface units or from a higher demultiplex interface. Data on these
pins are sampled on the active edge of the corresponding LRCKn.
LRCK[1:8]: Line Receive Clock for Framer 1 ~ 8
These pins receive externally recovered line clock (2.048 or 1.544 MHz). The clock is used to sample the data on
the corresponding LRDn.
RSCK[1:8]: Receive Side System Clock for Framer 1 ~ 8
In Receive Clock Master Full E1 or T1/J1 mode, the clock is a smoothed version of the corresponding 2.048 or
1.544 MHz Line Receive Clock (LRCKn). The RSCKn is pulsed for each bit in the 256-bit or 193-bit frame. The cor-
responding RSFSn and RSDn pins are updated on the active edge of RSCKn.
In Receive Clock Master Nx64K mode, the clock is a gapped version of the associated smoothed LRCKn. The
pulse number of RSCKn in each frame is controllable from 0 to 255 or from 0 to 192 on a per-timeslot/channel
basis. The corresponding RSFSn and RSDn pins are updated on the active edge of RSCKn.
In Receive Clock Slave RSCK Reference mode, RSCKn can be selected to be either a 2.048/1.544 MHz jitter atten-
uated version of the corresponding LRCKn or an 8KHz clock divided down from the smoothed line clock LRCKn.
RSSIG[1:8]: Receive Side System Signaling for Framer 1 ~ 8
In Receive Clock Slave External Signaling mode, the extracted signaling is output on these pins. The signal on
these pins is timeslot/channel-aligned with the data output on the corresponding RSDn pin and is updated on the
active edge of RSCCK. The extracted signaling is located in the lower nibble (b5 ~ b8). In E1 mode, the extracted
signaling repeats during the entire Signaling Multi-Frame for the same time slot. In T1/J1 mode, the extracted sig-
naling repeats during the entire SF/ESF for the same channel.
MRSSIG[1:2]: Multiplexed Receive Side System Signaling
When the multiplexed bus structure is configured, the extracted signaling data from the selected framers are multi-
plexed on these pins using a byte-interleaved multiplexing scheme. The data on MRSSIG[1:2] are updated on the
active edge of MRSCCK.
RSD[1:8]: Receive Side System Data for Framer 1 ~ 8
The processed data stream is output on these pins.
In Receive Clock Master mode, RSDn is updated on the active edge of the corresponding RSCKn.
In Receive Clock Slave mode, RSDn is updated on the active edge of RSCCK.
MRSD[1:2]: Multiplexed Receive Side System Data
When the multiplexed bus structure is configured, the processed data stream from the selected framers is multi-
plexed on these pins using the byte-interleaved multiplexing scheme. The data on MRSD[1:2] are updated on the
active edge of MRSCCK.
Line and System Interface
6
Description
T1 / E1 / J1 OCTAL FRAMER
March 5, 2009