IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 119

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
4.2.2
TEMODE (b0, 400H) is set to logic 1. Except for the setting of the JYEL
in bit 3 of FRMP Configuration registers (020H, 0A0H, 120H, 1A0H,
220H, 2A0H, 320H, 3A0H), the J1_YEL in bit 5 of ALMD Configuration
registers (02CH, 0ACH, 12CH, 1ACH, 22CH, 2ACH, 32CH, 3ACH) and
the J1_YEL in bit 5 and the J1_CRC in bit 6 of FRMG Configuration reg-
isters (044H, 0C4H, 144H, 1C4H, 244H, 2C4H, 344H, 3C4H), the set-
ting of the other registers is the same as the setting in T1 mode.
from the setting in the T1 mode.
ters (020H, 0A0H, 120H, 1A0H, 220H, 2A0H, 320H, 3A0H) to logic 1,
the Frame Processor will operate in J1 mode. Set the J1_YEL in bit 5 of
ALMD Configuration registers (02CH, 0ACH, 12CH, 1ACH, 22CH,
Table 52: Various Operation Modes in Receive Path for Reference
Operation
Reference Mode
Signaling Mode
Signaling Mode
Master Full T1/
Receive Clock
Receive Clock
Slave External
Receive Clock
Slave External
Receive Clock
(1.544 Mbit/s)
(2.048 Mbit/s)
Slave RSCK
J1 Mode
The IDT82V2108 can also be operated in J1 mode when the
The follows illustrate the setting in the J1 mode which is different
In receive path, set the JYEL in bit 3 of FRMP Configuration regis-
Mode
OPERATION IN J1 MODE
Register
02CH
02CH
02CH
02CH
001H
003H
020H
040H
001H
003H
020H
040H
001H
003H
020H
040H
001H
003H
020H
040H
1
Value (from Bit7 to Bit0)
10000000
00010011
00110000
00010000
00000100
11000000
00010011
00110000
00010000
00000100
11010000
00010011
00110000
00010000
00000100
01000000
00010000
00000000
00000000
00000000
In the Receive Clock Slave RSCK Reference mode.
Enable the normal operation of the RSDn pin. The data on RSDn is updated on the rising edge
of RSCCK. The data on RSCFS is sampled on the falling edge of RSCCK.
The Frame Processor is set in the ESF format. The CRC-6 calculation is performed when mimic
framing pattern is present.
The Alarm Detector is set in the ESF format.
The Receive CAS/RBS Buffer is set in the ESF format.
In the Receive Clock Slave External Signaling mode. The backplane rate is 1.544 Mbit/s.
Enable the normal operation of the RSDn and RSSIGn pins. The data on RSDn and RSSIGn is
updated on the rising edge of RSCCK. The data
of RSCCK.
The Frame Processor is set in the ESF format. The CRC-6 calculation is performed when mimic
framing pattern is present.
The Alarm Detector is set in the ESF format.
The Receive CAS/RBS Buffer is set in the ESF format.
In the Receive Clock Slave External Signaling mode. The backplane rate is 2.048 Mbit/s.
Enable the normal operation of the RSDn and RSSIGn pins. The data on RSDn and RSSIGn is
updated on the rising edge of RSCCK. The data on RSCFS is sampled on the falling edge of
RSCCK.
The Frame Processor is set in the ESF format. The CRC-6 calculation is performed when mimic
framing pattern is present.
The Alarm Detector is set in the ESF format.
The Receive CAS/RBS Buffer is set in the ESF format.
In the Receive Clock Master Full T1/J1 mode.
Enable the normal operation of the RSDn pin. The data on RSDn and RSFSn is updated on the
rising edge of RSCK.
The Frame Processor is set in the SF format.
The Alarm Detector is set in the SF format.
The Receive CAS/RBS Buffer is set in the SF format.
109
2ACH, 32CH, 3ACH) to logic 1, the Alarm Detector will operate in J1
mode.
registers (044H, 0C4H, 144H, 1C4H, 244H, 2C4H, 344H, 3C4H) to logic
1, the Frame Generator will generate J1 frame. Set the J1_YEL in bit 5
of FRMG Configuration registers (044H, 0C4H, 144H, 1C4H, 244H,
2C4H, 344H, 3C4H) to logic 1, the IDT82V2108 will transmit the Yellow
alarm in J1 format if Yellow alarm transmission is enabled.
4.2.3
ation modes can be set in the transmit path. In each operation modes,
the configurations in Table 52 and Table 53 are illustrated for reference.
In transmit path, set the J1_CRC in bit 6 of FRMG Configuration
Five operation modes can be set in the receive path and four oper-
VARIOUS OPERATION MODES CONFIGURATION
Description
on RSCFS is sampled on the falling edge
2
T1 / E1 / J1 OCTAL FRAMER
March 5, 2009